Abstract
A method for testing the interconnections of ordinary static RAMs with a processor that has a boundary-scan register and an IEEE 1149.1 test-access port is described. The method uses an enhanced boundary-scan-register design that manipulates the test-access-port controller states to meet the static RAM's timing constraints. The implementation is more economical than a boundary-scan register that strictly conforms to IEEE 1149.1. Test operation is more efficient, requiring a third of the number of scan operations. A test-pattern set and a method for detecting and diagnosing the interconnection faults on RAMs are also described. The test-pattern set can be enhanced as necessary to increase coverage and diagnosing ability and to handle any RAM configuration. The implementation of the proposed boundary-scan register is independent of the test algorithm used. It is believed that the methodology is extendable to RAMs that use an access protocol different from the one described, for example dynamic RAMs and synchronous RAMs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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