Abstract
The testability distribution of a VLSI circuit can be used to predict the fault coverage of a set of test patterns by restricting the standard test pattern generation process to a sample of faults. When testability of a VLSI circuit is modeled as a beta distribution, the random detection counts obtained have a beta-binomial distribution. This paper includes: a) three confidence intervals for the parameters of the beta-binomial distribution; b) a determination of the proper sample size needed such that the theoretical confidence intervals agree with the actual ones; and c) a determination of the effect of the number of generated tests on confidence interval widths. Restricting the test generation process to a sample of faults results in major savings in the overall costs of test generation. Experimental results are given on three of the large combinational benchmark circuits (presented at the 1985 International Symposium on Circuits and Systems).
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