Semiconductor Device Processing Research Articles

Transfer-free rapid growth of 2-inch wafer-scale patterned graphene as transparent conductive electrodes and heat spreaders for GaN LEDs

A technique for the transfer-free growth of 2-inch wafer-scale patterned graphene directly on GaN LED epilayers is introduced. High-quality graphene as transparent electrodes and heat spreaders is synthesized directly on GaN by PECVD at only 600 °C deposition temperature and within 3 min growth time. Co acts as both the catalyst for graphene growth and the dry etching mask for GaN mesas, which greatly improves the efficiency of the semiconductor device process. Elegantly, the graphene growth is in accordance with the shape of Co, which offers a lithography-free patterning technique of the graphene. Afterward, using our penetration etching method through the PMMA and graphene layers, the Co is peacefully removed, and in-situ Ohmic contact is achieved between the graphene and p-GaN where the contact resistivity is only 0.421 Ω cm2. The graphene sheet resistance is as low as 631.2 Ω sq−1. The device is also superior to the counterpart graphene-free LED in terms of heat spreading behavior, as evidenced by the lower junction temperature and thermal resistance. Most importantly, the developed technique produces graphene with excellent performance and is intrinsically more scalable, controllable, and semiconductor industry compatible than traditionally transferred graphene.

Ternary mixed crystal effects on optical phonons in wurtzite ZnO quantum wells with asymmetric MgZnO barriers

Optical phonons significantly relate to fundamental limits on dynamical processes in layered polar semiconductor devices. MgZnO layers commonly serve as barriers of ZnO quantum wells (QWs) to improve the electric and optical properties by quantum confinement while keeping the Mg fraction below 0.4 to avoid the crystal phase transformation from wurtzite to rocksalt. This work investigates ternary mixed crystal effects on optical phonons in wurtzite ZnO quantum well with asymmetric barriers of MgxZn1-xO and MgyZn1-yO over a full range of Mg mole fractions. Since MgZnO could be wurtzite (WZ) and rocksalt (RS) phases, the QWs can be denoted as WZ/WZ/WZ, WZ/WZ/RS, and RS/WZ/RS, respectively. Both asymmetries in the Mg fractions and crystal structures of the two barriers affect the optical phonons in QWs. RS/RS/RS quantum wells are also discussed for comparison. Since oscillatoring electrostatic potential of optical phonons is only permitted in the anisotropic wurtzite but forbidden in istropic rocksalt, more modes of confined optical phonons are found in a WZ/WZ/WZ QW, followed by WZ/WZ/RS one, and the least in the RS/WZ/RS one, while there is no confined optical phonons in RS/RS/RS quantum wells. Besides, the difference between the Mg fractions in two barriers leads to more modes of interface optical phonons due to the two unequal interfaces. The modes contained in the optical phonons spectra as well as their frequency ranges, dispersion relations, and electrostatic potentials, vary with Mg fraction in barriers. The strain on interfaces induced by the lattice mismatch leads to a slight blue shift of the dispersion relation as Mg fraction increases. Based on the results of this paper, the optical phonons related to electronic and optoelectronic properties in QWs could be further understood and adjusted.

Wafer-Scale Graphene Growth on Si/SiO2 Substrates via Metal-Free Chemical Vapor Deposition

The direct growth of graphene on an insulator plays a crucial role in various applications, such as optoelectronic devices, supercapacitors, sensors, and so on. However, how to synthesize large area, homogeneous monolayer graphene with high quality remains a primary challenge. How to evaluate the flake size of directly grown graphene from a macroscopic perspective is yet to be explored. Herein, a full monolayer wafer-scale graphene film covering a silicon/silicon oxide substrate was realized via atmospheric pressure chemical vapor deposition under an optimized temperature, growth time, and methane flow rate. Both the Raman mapping and AFM characterization confirm that a homogeneous monolayer graphene was obtained (I2D/IG = 4.89, FWHM2D = 19.08). The transfer-free graphene exhibited a Hall mobility of 1864.6 cm2·V–1·S–1. Moreover, an empirical formula has been developed by applying the Monte Carlo method with the measured results to reflect the dependence of the resistivity of the graphene film on its flake size distributions as ρ=ρ01−k(1d2)0.4835. This work is highly compatible with present semiconductor device processing techniques and is expected to be highly desirable for Si-based graphene applications.

Correlative microscopy and monitoring of segregation processes in optoelectronic semiconductor materials and devices

The present work comprises a practical tutorial on the topic of correlative microscopy and its application to optoelectronic semiconductor materials and devices. For the assessment of microscopic structure–property relationships, correlative electron microscopy, combined also with scanning-probe and light microscopy, exhibits a collection of indispensable tools to analyze various material and device properties. This Tutorial describes not only the various microscopy methods but also the specimen preparation in detail. Moreover, it is shown that electron microscopy can serve to monitor phase segregation processes on various length scales in semiconductor nanoparticles and thin films. Algorithms used to extract phase information from high-resolution transmission electron micrographs are explained.

Data-driven Prognostic Approaches for Semiconductor Manufacturing Process: A Review of Recent Works and Future Perspectives

The manufacturing process of semiconductor devices is one of the most complex processes in manufacturing industry. The devices fabrication is performed through hundreds of sequential process steps with different recipes. The level of complexity is also increasing due to the high demands in terms of feature size and number of devices. Maintaining high yield and good quality production are the main objectives of these industries. These objectives can be achieved by adopting efficient maintenance strategies. In this context, a suitable prognostic model is required in order to schedule the maintenance actions. Among the different prognostic approaches, data-driven ones received a lot of attention since they do not require any specific knowledge for modeling these complex processes. Although the advances in data-driven prognostic works, there is a real lack of survey papers that overview and discuss the existing approaches for this industry over the past 10 years. Therefore, this paper presents a systematic overview of data-driven prognostic for semiconductor manufacturing. It investigates the different used methods, the challenges of their application and the unexplored research areas.

(Invited) Photoelectrochemical Processing of Semiconductor Devices

Many of the chemical processes used to fabricate and metallize semiconductor devices are based on oxidation-reduction reaction. Electro-chemical processes using the semiconductor itself have the advantage of being able to photo-generate the reactants within the semiconductor to carryout local reactions. The development of photoelectrochemical methods to process features in semiconductor devices is a subject unique to the Electrochemical Society because it is at the intersection of electrochemistry and semiconductor device fabrication. Specific symposia at ECS meeting have explored these subjects. In particular, Noel Buckley was a motivating force behind the State-of-the-Art Program on Compound Semiconductors (SOTAPOCS) symposium series which offered venues for presenting interdisciplinary results of this kind. In this talk, several examples of chemical and photoelectrochemical processes for semiconductor device manufacturing from past ECS SOTAPOCS symposia, organized by Noel Buckley, will be described.

Roentgen radiation response in P-N semiconductor device

Radiation is an important for investigate semiconductor device process improvement area. Currently, radiation use for many areas in semiconductor device and one of application use semiconductor device for detector. However, radiation is one of part of cure process in semiconductor area although radiation has high energy and may impact to semiconductor device performance. The experiment of radiation exposed on semiconductor device investigate radiation impact area on device by COMSOL simulation before fabricate semiconductor diode. COMSOL results show high temperature on active area of semiconductor device while exposed with SRFE process that may impact to device mechanism and electrical properties of device.

Effects of COVID-19 on a CMOS fabrication course: An integrated design experience.

In the CMOS fabrication course described herein, the lecture component provides the theoretical background for semiconductor materials and integrated circuit fabrication processes. The laboratory component provides the hands‐on experience required to fabricate and electrically characterize CMOS circuits in a one‐semester format. A strong semiconductor device process design thread is achieved in the course by integrating the laboratory experience and process simulation/modeling and theoretical calculations. The risks associated with the COVID‐19 pandemic have forced significant course modifications. The lecture is switched to a remote learning format, including pre‐recorded content and weekly advanced Q&A sessions. The laboratory provides both in‐person and remote sessions. Approved social distancing and cleaning protocols are practiced in the facility for in‐person learning. Complementary remote learning resources are made available to all the students such as pre‐recorded laboratory instructions, live video‐based laboratory sessions, and web‐based supplementary information. Compared to pre‐pandemic semesters, the average students' GPA of the pandemic period has increased, attributed to larger and archived volumes of instructional material. Overall student comments related to course changes necessitated by the pandemic are mixed with both positive and negative feedback.

Foreword Special Issue on “New Simulation Methodologies for Next-Generation TCAD Tools”

Technology computer-aided design (TCAD) is an integral part of the development process of semiconductor technologies and devices, a field which has become increasingly complex and heterogeneous. Processing of integrated circuits requires nowadays over 400 process steps, and the resulting devices often have an intricate 3-D structure and contain various specifically designed materials. The full device behavior can only be understood by considering effects on all length scales from atomistic (material properties, interfaces, defects, and so on), to nanometric (quantum confinement, non-bulk properties, tunneling, ballistic transport, and so on), to full-chip dimensions (strain, heat transport, and so on), and time scales from femtoseconds (scattering, ferroelectric switching time, and so on) to seconds (trapping times, degradation, and so on). Voltages, currents, and charges have been scaled to such low levels that statistical effects and process variations have a strong impact. Devices based on new materials (e.g., 2-D crystals) and physical principles (ferroelectrics, magnetic materials, qubits, and so on) challenge standard TCAD approaches. While the simulation methods developed by the physics community can describe the basic device behavior, they often lack important simulation capabilities like, for example, transient simulations or integration with other TCAD tools, and are often too slow for daily use. Due to the complexity of semiconductor technology, it becomes more and more difficult to assess the impact of a change in processing or device structure on circuit performance by looking at a single aspect of an isolated device under idealized conditions. Instead, a TCAD tool chain is required which can handle realistic device structures embedded in a chip environment. New methodologies are required for all aspects of TCAD to ensure an efficient tool chain covering from atomistic effects to circuit behavior based on flexible simulation models that can handle new materials, device principles, and the ensuing large-scale simulations and that make use of artificial intelligence for well-chosen (sub)routines to decrease the overall simulation time. This Special Issue features six invited and 18 regular papers that address these problems.

A Mechanistic Study of the HF Pulse in the Thermal Atomic Layer Etch of Crystalline and Amorphous HfO2

HfO2 is a high-k material that is crucial in semiconductor devices. Atomic-level control of material processing is required for the fabrication of thin films of this material at nanoscale device sizes. Atomic layer deposition (ALD) and thermal atomic layer etching (ALE) allow the fabrication of ultra-thin films for semiconductor device processing. ALD is a well-known metal oxide thin film deposition technique that enables a high level of control over film thickness. Thermal ALE, which is growing in importance, uses self-limiting halogenation (e.g. HF exposure) producing a non-volatile modified layer. Subsequent ligand exchange reactions remove up to a monolayer of the metal oxide. This modern approach for controlled etching is the reverse of ALD. In gate oxides, the use of amorphous materials is better than crystalline films as the lack of grain boundaries allow for a high breakdown voltage. Amorphous materials have a lower density than crystalline materials.Experimental studies have shown that HfO2 amorphous films have higher etch rates per cycle than crystalline HfO2 films regardless of the fluorination reactant. Given that it is difficult to investigate ALE reactions directly using experimental techniques, first-principles-based atomic-level simulations using density functional theory (DFT) can give deep insights into the precursor chemistry and the reactions that drive the etch of different materials. This contribution presents first-principles density functional theory modelling to examine the etch chemistry of crystalline and amorphous films of HfO2. HF molecules adsorb on the surface of HfO2 by forming hydrogen bonds and may remain intact or dissociate to form Hf-F and O-H bonds. The adsorption of one HF molecule at the bare surface of both the crystalline and amorphous models results in dissociative adsorption at all binding sites. For multiple HF adsorption, we find mixed molecular and dissociative adsorption of HF molecules at the bare surfaces of the crystalline and amorphous models of HfO2. We also present a thermodynamic analysis approach to compare reaction models representing the self-limiting (SL) and continuous spontaneous etch (SE) processes taking place during an ALE pulse.

The effect of the chuck shape on the wafer topography in back grinding of wafer with outer rim

Back Grinding of Wafer with Outer Rim (BGWOR) is a novel method for carrier-less thinning of silicon wafers. Silicon wafers are widely used in integrated circuits (ICs). The topography of the wafer will not only directly affect the efficiency of subsequent processing of semiconductor devices, but correspondingly affect the performance and life of these devices. However, there are few studies on the shape of the ground wafer in BGWOR. In this paper, the mathematical model of the wafer topography in BGWOR was developed. With this model, the radial thickness and total thickness variation (TTV) of a wafer under different parameters, including inclination angles and radii of grinding wheel for dressing chuck, were simulated by MATLAB. Inclination angles and radii of grinding wheels for the dressing chuck had a great influence on the radial thickness and TTV of a wafer in the BGWOR. Lastly, the pilot experiments were conducted to validate the theoretical model of grinding topography and TTV of the wafer in BGWOR. To enhance the flatness of the ground wafer, it is essential to control the shape of the dressing chuck. The research results are helpful to the optimization of the dressing process of the chuck in the BGWOR.

The stability of Cl-, Br-, and I-passivated Si(100)-(2 × 1) in ambient environments for atomically-precise pattern preservation

Atomic precision advanced manufacturing (APAM) leverages the highly reactive nature of Si dangling bonds relative to H- or Cl-passivated Si to selectively adsorb precursor molecules into lithographically defined areas with sub-nanometer resolution. Due to the high reactivity of dangling bonds, this process is confined to ultra-high vacuum (UHV) environments, which currently limits its commercialization and broad-based appeal. In this work, we explore the use of halogen adatoms to preserve APAM-derived lithographic patterns outside of UHV to enable facile transfer into real-world commercial processes. Specifically, we examine the stability of H-, Cl-, Br-, and I-passivated Si(100) in inert N2 and ambient environments. Characterization with scanning tunneling microscopy and x-ray photoelectron spectroscopy (XPS) confirmed that each of the fully passivated surfaces were resistant to oxidation in 1 atm of N2 for up to 44 h. Varying levels of surface degradation and contamination were observed upon exposure to the laboratory ambient environment. Characterization by ex situ XPS after ambient exposures ranging from 15 min to 8 h indicated the Br– and I–passivated Si surfaces were highly resistant to degradation, while Cl–passivated Si showed signs of oxidation within minutes of ambient exposure. As a proof-of-principle demonstration of pattern preservation, a H–passivated Si sample patterned and passivated with independent Cl, Br, I, and bare Si regions was shown to maintain its integrity in all but the bare Si region post-exposure to an N2 environment. The successful demonstration of the preservation of APAM patterns outside of UHV environments opens new possibilities for transporting atomically-precise devices outside of UHV for integrating with non-UHV processes, such as other chemistries and commercial semiconductor device processes.

Diamond-Incorporated Flip-Chip Integration for Thermal Management of GaN and Ultra-Wide Bandgap RF Power Amplifiers

GaN radio frequency (RF) power amplifiers offer many benefits including high power density, reduced device footprint, high operating voltage, and excellent gain and power-added efficiency. Accordingly, these parts are enabling next-generation technologies such as fifth-generation (5G) base transceiver stations and defense/aerospace applications such as high-performance radar and communication systems. However, these benefits can be overshadowed by device overheating that compromises the performance and reliability. In response to this, researchers have focused on GaN-on-diamond integration during the past decade. However, manufacturability, scalability, and long-term reliability remain as critical challenges toward the commercialization of the novel device platform. In this work, a diamond-incorporated flip-chip integration scheme is proposed that takes advantage of existing semiconductor device processing and growth techniques. Using an experimentally validated GaN-on-SiC multifinger device model, the theoretical limit of the cooling effectiveness of the device-level thermal management solution has been evaluated. Simulation results show that by employing a ~ 2-μm diamond passivation overlayer, gold thermal bumps, and a commercial polycrystalline carrier wafer, the power amplifier's dissipated heat can be effectively routed toward the package, which leads to a junction-to-package thermal resistance lower than GaN-on-diamond high electron mobility transistors (HEMTs). Furthermore, simulation results show that this approach is even more promising for lowering the device thermal resistance of emerging ultra-wide bandgap devices based on β-Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> and AlGaN, below that for today's state-of-the-art GaN-on-diamond HEMTs.

Chemical Dopant‐Free Doping by Annealing and Electron Beam Irradiation on 2D Materials

AbstractDoping is a key technique for forming complementary metal‐oxide‐semiconductor (CMOS) that is a basic building block for current state‐of‐the‐art semiconductor devices. However, conventional doping methods such as ion implantation are unsuitable for 2D materials due to their ultra‐thinness to accommodate substitutionally doped atomic structures and vulnerability to high energy ion bombardment. Chemical doping methods have been widely used for 2D materials to induce a charge exchange transfer; however, they are subjected to surface contamination which can be detrimental for high quality semiconductor device processing. In this work, the authors reveal the effects of chemicals‐free doping in which annealing induces a p‐doping effect by physisorption and substitution of oxygen atoms while electron beam irradiation selectively n‐dopes MoTe2, based on the results obtained by electrical characterization and Kelvin probe force microscopy. The annealing increases work‐function of MoTe2 which undergoes oxidation as observed in the reduction of surface potential and the transition of transfer curves toward the p‐type behavior. Electrical measurements and a significant reduction in surface potential after electron beam irradiation indicate the generation of trapped charges which is responsible for the n‐doping effect. Subsequently, the authors fabricate a CMOS inverter consisting of distinctively p‐ and n‐doped areas of MoTe2.

Review of Silicon Photonics Technology and Platform Development

Many breakthroughs in the laboratories often do not bridge the gap between research and commercialization. However, silicon photonics bucked the trend, with industry observers estimating the commercial market to close in on a billion dollars in 2020 <xref ref-type="bibr" rid="ref45">[45]</xref>. Silicon photonics leverages the billions of dollars and decades of research poured into silicon semiconductor device processing to enable high yield, robust processing, and most of all, low cost. Silicon is also a good optical material, with transparency in the commercially important infrared wavelength bands, and is a suitable platform for large-scale photonic integrated circuits. Silicon photonics is therefore slated to address the world&#x0027;s ever-increasing needs for bandwidth. It is part of an emerging ecosystem which includes designers, foundries, and integrators. In this paper, we review most of the foundries that presently enable silicon photonics integrated circuits fabrication. Some of these are pilot lines of major research institutes, and others are fully commercial pure-play foundries. Since silicon photonics has been commercially active for some years, foundries have released process design kits (PDK) that contain a standard device library. These libraries represent optimized and well-tested photonic elements, whose performance reflects the stability and maturity of the integration platforms. We will document the early works in silicon photonics, as well as its commercial status. We will provide a comprehensive review of the development of silicon photonics and the foundry services which enable the productization, including various efforts to develop and release PDK devices. In this context, we will report the long-standing efforts and contributions that previously IME&#x002F;A^&#x002A;STAR and now AMF has dedicated to accelerating this journey.

Modelling the Growth and Etch of Thin Film Metal Oxides

HfO2 and ZrO2 are two high-k materials that are crucial in semiconductor devices. Atomic level control of material processing is required for fabrication of thin films of these materials at nanoscale device sizes. Atomic layer deposition (ALD) and thermal atomic layer etching (ALE) allow fabrication of ultra-thin films for semiconductor device processing. ALD is a well-known metal oxide thin film deposition technique in which metal and oxygen containing precursors are added sequentially to the reactor to ensure self-limiting precursor adsorption and reaction to enable a high level of control over film thickness. Thermal ALE, which is a relatively modern technique, uses self-limiting fluorination (using hydrogen fluoride exposure) and subsequent ligand exchange reactions at elevated temperatures to remove up to a monolayer of the metal oxide material. This modern approach for controlled etching is the reverse of ALD and removes only the fluorinated layer.Given that it is difficult to investigate ALD and ALE reactions directly using experimental techniques, first-principles-based atomic-level simulations using density functional theory (DFT) can give deep insights into the precursor chemistry and the reactions that drive the deposition and etch of different materials. This contribution presents first principles density functional theory modelling to examine the growth and etch of thin films of HfO2 and ZrO2. Concerning the ALD reaction, the adsorption mechanism of precursors TDMAHf and TDMAZr are studied at the bare and hydroxylated surfaces of HfO2 and ZrO2 respectively. Stable OH coverages of 0.50 ML and 0.63 ML on the surfaces of HfO2 and ZrO2 were found respectively. Ligand loss from the metal precursor can be achieved by protonation from the OH terminated surface of both metal oxides. Concerning the ALE reaction, HF exposures on the surfaces of HfO2 and ZrO2 are studied. HF coverages ranging from 1.0 ± 0.3 to 17.0 ± 0.3 HF/nm2 are investigated and a mixture of molecularly and dissociatively adsorbed HF molecules is present at higher coverages. Theoretical etch rates of -0.61 ± 0.02 Å /cycle for HfO2 and -0.57 ± 0.02 Å /cycle ZrO2 were calculated using maximum coverages of 7.0 ± 0.3 and 6.5 ± 0.3 M-F bonds/nm2 respectively (M = Hf, Zr).

Nanoscale Bilayer Mechanical Lithography Using Water as Developer.

Sustainability has become a critical concern in the semiconductor industry as hazardous wastes released during the manufacturing process of semiconductor devices have an adverse impact on human beings and the environment. The use of hazardous solvents in existing fabrication processes also restricts the use of polymer substrates because of their low chemical resistance to such solvents. Here, we demonstrate an environmentally friendly mechanical, bilayer lithography that uses just water for development and lift-off. We show that we are able to create arbitrary patterns achieving resolution down to 310 nm. We then demonstrate the use of this technique to create functional devices by fabricating a MoS2 photodetector on a polyethylene terephthalate (PET) substrate with measured response times down to 42 ms.

Practice and Exploration of Engineering Case Teaching of Microelectronics Technology Specialty in Higher Vocational Colleges

Microelectronics technology major is a strong professional and practical engineering specialty in higher vocational colleges, which involves the design and manufacturing process of semiconductor devices and integrated circuits and other related professional knowledge, and has higher requirements for practical teaching conditions. Therefore, higher vocational colleges are facing certain challenges in the teaching process. With the deepening of education reform, engineering case teaching is gradually becoming mature, especially in this kind of typical engineering specialty with significant teaching effect. This paper mainly discusses the engineering case teaching practice of microelectronics technology specialty in higher vocational colleges. Starting from the characteristics and functions of engineering case teaching, it explores a practical and effective engineering case teaching mode, actively introduces typical engineering case teaching, and continuously optimizes the course teaching mode, as well as improves the quality and effect of engineering case teaching for microelectronics technology specialty.

Crystal plasticity analysis of the suppression of dislocation accumulation during the production process of semiconductor devices

Crystal plasticity analysis of the suppression of dislocation accumulation during the production process of semiconductor devices

Suspended single-crystalline oxide structures on silicon through wet-etch techniques: Effects of oxygen vacancies and dislocations on etch rates

Wet-etch techniques to realize suspended microscale structures of single-crystalline SrTiO3 and BaTiO3 grown on Si are explored. The authors examine the effects of oxygen vacancies and dislocations on etch rates. Both oxygen vacancies and dislocations enhance etching, yielding rates that are sufficiently high to enable conventional photoresist to serve as a mask layer. Suspended bridge structures are realized by etching the underlying Si substrate using a potassium hydroxide solution. The ability to realize suspended microscale structures using wet-etch techniques that are compatible with standard semiconductor device processing opens a pathway to integrate multifunctional oxides in microelectromechanical systems.