Semiconductor Device Processing Research Articles

Gap-Fill Process of Shallow Trench Isolation for 0.13 µm Technologies

Gap-fill technology using high-density plasma chemical vapor deposition (HDP-CVD) is one of the leading technologies in 0.13 µm generation semiconductor device processing. The analysis of the dependence of HDP-CVD filling characteristics on the processes used revealed that film deposition under an increased plasma power and low-pressure conditions is effective for stable gap filling. By optimizing these process parameters, we were able to implement shallow trench isolation (STI) of space width 0.13 µm and aspect ratio 3.9. Furthermore, we demonstrated that the angular dependence of sputter yield and the ionic deposition mechanism are important factors when performing filling by means of HDP-CVD. The filling characteristics can be improved by increasing the maximum sputter yield angle and the amount of ionic deposition component. Based on these mechanisms, we constructed a topography simulation model which enables accurate expression of the topography of the HDP-CVD film.

内周刃スライシングにおけるチッピングの低減化と加工液の影響

At the edge portion of the wafer sliced in ID-Blade sawing, edge-chippings are usually broken out. This has become an important factor which should be improved in the manufacturing process of semiconductor devices. This study aims to reduce the edge chipping size by means of utilizing slurry which mixed a little free abrasive grains into the working fluid. This method brought the buffer effect between diamond grains adhered to the ID-Blade and the edge portion of workpiece. In this paper, reduction of the edge-chipping utilized slurry and influence of engage and disengage angle of ID-Blade to the workpiece are described. Consequently, edge-chipping size at the edge portion of the wafer was reduced compared with the case in which usual working fluid is used and it became small when an engage and disengage angle are shallow.

Thin film atomic layer deposition equipment for semiconductor processing

Atomic layer deposition (ALD) of ultrathin high-K dielectric films has recently penetrated research and development lines of several major memory and logic manufacturers due to the promise of unprecedented control of thickness, uniformity, quality and material properties. LYNX-ALD technology from Genus, currently at beta phase, was designed around the anticipation that future ultrathin materials are likely to be binary, ternary or quaternary alloys or nanolaminate composites. A unique chemical delivery system enables synergy between traditional, production-proven low pressure chemical vapor deposition (LPCVD) technology and atomic layer deposition (ALD) controlled by sequential surface reactions. Source chemicals from gas, liquid or solid precursors are delivered to impinge on reactive surfaces where self-limiting surface reactions yield film growth with layer-by-layer control. Surfaces are made reactive by the self-limiting reactions, by surface species manipulation, or both. The substrate is exposed to one reactant at a time to suppress possible chemical vapor deposition (CVD) contribution to the film. Precisely controlled composite materials with multiple-component dielectric and metal–nitride films can be deposited by ALD techniques. The research community has demonstrated these capabilities during the past decade. Accordingly, ALD equipment for semiconductor processing is unanimously in high demand. However, mainstream device manufacturers still criticize ALD to be non-viable for Semiconductor device processing. This article presents a broad set of data proving feasibility of ALD technology for semiconductor device processing.

半導体のトランスファー成形工程における金線変形予測手法の検討 第３報 ＢＧＡパッケージとＱＦＰでの共通パラメーターの構築

A practical method for predicting gold-wire deformation during the transfer molding process of semiconductor devices has been developed. In this study, common parameters for estimating values of wire deformation of the BGA (Ball Grid Array) package and the QFP (Quad Flat Package) used in previous reports were investigated. First, we examined the parameter λ, which was already derived as a function of resin velocity component perpendicular to the center of each wire, resin flow time at the center of each wire, apparent resin viscosity in the mold cavity, gold wire dimensions such as loop height, actual length and diameter, and Young's modulus for the gold wire. In the case of the BGA package, the maximum horizontal displacement, δmax, was found to be a linear function of λ up to around δmax=0.4mm with an intersection at the origin of the coordinate axes, On the other hand, for the QFP, a deviation from linearing was found for δmax exceeding 0.16mm. Next, both δmax and λ were divided by the actual length of each gold wire, and these values were defined as new parameters ζ and φ, respectively. By introducing these parameters, all the data were found to fit well by a straight line up to around ζ=8% with a subsequent a saturation curve. Three empirical models to represent the relationship between ζ and φ were obtained. Using these models, values of ζ were accurately calculated.

152 半導体製造プロセスにおける超微細塗布技術の開発(マイクロエネルギー/精密機器マイクロメカトロニクス)

Nowadays, the needs of micro dispensing technologies increase with the spread of the handy terminals. In mounting process of semiconductor devices, micro dispensing apparatus has to be indispensable in spite of the demerit for the low productivity. In order to improve the dispensing speed and the accuracy for the micro dispensing paste are examined. This paper describes about the factors on accurate dispensing in mounting the small chip components.

Interplay Between Copper Electroplating and Chemical Mechanical Planarization

The introduction of Chemical Mechanical Polishing (CMP) into semiconductor device processing brought a significant need for wet chemistry research and development in this industry. With the transition from aluminum to copper for advanced interconnect metallization came a tremendous amount of electrochemical research and process development towards a production worthy copper CMP process capable of meeting the stringent specifications of dual damascene integration.In addition, the dual damascene integration scheme introduced copper deposition challenges that brought significant activity in developing another wet chemistry process, electroplating. These two sequential, chemical processes have been shown to have significant interaction that has created significant challenges in process integration.

In situ electrical characterization of dielectric thin films directly exposed to plasma vacuum-ultraviolet radiation

In this article we report a method for in situ electrical characterization of dielectric thin films under direct exposure to plasma in an electron-cyclotron-resonance etcher. This method is based on the development of a special test structure that allows for the measurement of the influence of plasma vacuum-ultraviolet (VUV) radiation on the electrical conductivity of thin dielectric layers. Results show that the measured conductivity of SiO2 layers temporarily increases during exposure to argon and oxygen plasmas, with controlled VUV emission. Based on the measurements made through this method, a model of the VUV-induced conductivity of SiO2 is developed. These measurements are very important for plasma processing of semiconductor devices, because the temporary increase in the conductivity of these layers upon exposure to processing plasmas can decrease the plasma-induced charging of these dielectric layers depending on the intensity of the plasma VUV emission. This can have an impact on the properties and reliability of processed devices.

Relaxation-time approximations of quasi-hydrodynamic type in semiconductor device modelling

We analyse mathematical models for the description of carrier transport in semiconductors as a hierarchy of models constructed on the basis of the relaxation-time concept. In this hierarchy we focus on a reasonable compromise between drift-diffusion, hydrodynamic, and kinetic models. This compromise is provided by non-local quasi-hydrodynamic mathematical models describing non-equilibrium physical processes in semiconductor devices. Details of the normalization procedure for the quasi-hydrodynamic system will be given along with a transformation of the energy-balance equations to provide computationally convenient forms.

Modelling nonlocal processes in semiconductor devices with exponential difference schemes

In this paper nonlocal quasi-hydrodynamic mathematical models describing non-equilibrium physical processes in semiconductor devices are considered. These processes cannot be adequately described with conventional drift-diffusion models. The primary numerical difficulty arises in the energy balance equation. Details of the discretisation for the continuity equations will be described along with a transformation of the energy balance equations to give computationally convenient forms. Effective exponential difference schemes are constructed and applied to modelling transport phenomena in semiconductors. Stability conditions, computational convergence and algorithmic realisations of the proposed schemes are discussed and numerical examples are given.

半導体のトランスファー成形工程における金線変形予測手法の検討 第２報 ＱＦＰで金線諸元を変えた解析

A practical method for predicting gold-wire deformation during the transfer molding process of semiconductor devices has been developed. In this study, a QFP (Quad Flat Package) having 160 wires was used. The deformed configuration and maximum deformed values were measured for different configurations of the gold wires. Horizontal, dimensionless, and deformed configurations of gold wires could be characterized by elastic straight beams under the conditions of end supports and center load. By combining the results of this study with those of a previous report on the BGA (Ball Grid Array) package, we were able to establish a relationship between the parameter λ and the resin velocity component perpendicular to the center of each wire, resin flow time at the center of each wire, apparent resin viscosity in the mold cavity, gold wire dimensions such as loop height, actual length and diameter, and Young's modulus for the gold wire. The relationship between λ and the maximum horizontal displacement, δmax was described by a combination of a straight line from the origin of the coordinate axes leading to a saturation curve. For the linear region, an empirical equation model to estimate δmax was obtained.

半導体のトランスファー成形工程における金線変形予測手法の検討 第１報 ＢＧＡパッケージで金線諸元を固定した解析

A practical method for predicting gold-wire deformation in the transfer molding process of semiconductor devices has been developed. In this study, a BGA (Ball Grid Array) package having 156 wires with uniform dimensions was used. Horizontal, dimensionless, and deformed configurations of gold wires were found to be the same as those of elastic straight beams under the conditions of end supports and center load. An empirical model having parameters of the resin velocity component perpendicular to the center of each wire, resin flowing time at the center of each wire, and apparent resin viscosity in a mold cavity was formulated. Using this model, maximum values of the deformation of every gold wire in the package at several molding conditions were calculated accurately.

A Study of Fixing Force for a Work Utilized Vacuume in Ultrasonic Wire Bonders.

In an assembling process of semiconductor devices, many kinds of ultrasonic wire bonders are generally used. In these machines, works are usually placed on a plate with small vacuum suction hole(s) to hold the works against ultrasonic bonding vibration. In terms of bonding condition, bonding points are required to be fixed firm enough to avoid miss bonding. This study was carried out to estimate the holding force of the vacuum suction methods. Some equations were derived to calculate the suction force and the friction moment of a work placed on a plate with a circular or rectangular vacuum hole under and assumed linear pressure distribution. Furthermore basing upon the Reynolds equation, some negative pressure distributions and the holding force of a work were calculated by the FEM. These results were compared, and an approximate correction function was found for the expressions derived. These results were proved to be valid from experiments.

In-situ characterization technique of compound semiconductor heterostructure growth and device processing steps based on UHV contactless capacitance-voltage measurement

In this paper, the applicability of an ultra-high vacuum (UHV) contactless capacitance-voltage ( C-V) measurement method is evaluated for use in non-destructive characterization of crystal growth and device processing steps for the compound semiconductor heterostructure microelectronics. The UHV gap length between the sample surface and the field plate was made by an optical measurement using the Goos–Haenchen effect, and its accuracy was discussed by a theoretical calculation. Then, zero-bias position of the surface Fermi level, conduction type and doping were successfully determined on free surfaces of GaAs and InP by basic C-V measurements. Finally, the technique was applied to characterize each step of the UHV-based surface passivation process for InP utilizing the Si interface control layer (Si ICL). Change of the surface state distribution after each step was successfully detected without breaking UHV, demonstrating the powerful capability of the method.

In-Situ monitoring of temperature and alloy composition of Hg1−xCdxTe using FTIR spectroscopic techniques

Optical real-time in-situ sensors play a very important role in the processing of semiconductor devices because of their noncontact remote nature and excellent compatibility with UHV systems. In this work, we report on progress in developing an in-situ temperature sensor for HgCdTe structures grown by molecular beam epitaxy (MBE). Based on the Fourier transform infrared (FTIR) spectrometer, this sensor is capable of continuous real-time monitoring of the surface temperature, thickness and alloy composition of HgCdTe epilayers. The accuracy and sensitivity of this FTIR technique were studied in all temperature ranges of interest. Also compared are two different methods of temperature determination obtained from the normalized spectral radiance. The influence of stray radiation and of sample holder rotation on the measurement accuracy have been studied. Reflectivity spectra for HgCdTe/CdZnTe(211) and HgCdTe/CdTe(211)/Si(211) structures have been analyzed in real time in order to determine the layer thickness and alloy composition for growing layers. Also discussed is a multilayer-structure optical model developed to solve the problem of composition determination at early stages of growth. The application of this model for fitting the transmission spectra is demonstrated.

Grown‐in Oxide Precipitate Nuclei in Czochralski Silicon Substrates and Their Role in Device Processing

Using a method to study the grown‐in defect density spectra in Czochralski silicon wafers, we elucidate the changes in the size distribution of grown‐in oxide precipitate nuclei caused by thermal processing in a common complementary metal‐oxide semiconductor device process. The first thermal step determines which parts of the grown‐in defects grow to large stable defects and how many harmful defects appear in the defect‐denuded zone. The cooling rate of the crystal considerably influences the defect evolution during complementary metal oxide semiconductor processing. The choice of appropriate silicon material for a device process or adjusting processing conditions to suit the material are important for defect generation during processing and, consequently, also for device yield. © 1999 The Electrochemical Society. All rights reserved.

Recent results of multi-cathode electron beam plasma source

The basic experiments of the multi-cathode electron beam plasma source (MCEBPS) were carried out recently. The MCEBPS has characteristics of uniform plasma in large area. It can be extended to produce uniform plasmas in a very large diameter of several meter with addition of the other cathodes. The plasmas are made through direct interaction of electrons and neutral gases in the wide area with a diameter of 300 mm or above. The non-uniformity of the radial plasma density must be small to be suitable for the process of next generation semiconductor devices. The MCEBPS now has seven cathodes (multi-cathode) whose array is concentric to produce uniform plasmas in a large area at the target position. The energy of extracted electron beam from cathodes is about 50 eV. This can be controlled by changing the voltages of extraction electrodes. The electron beam current can be also controlled to the desired value by adjusting the cathode temperatures. The energy and the current of the electron beam can be controlled independently. In the working chamber, plasmas for the process of target material are produced through the direct interaction of the extracted electron beam and the neutral gases which are fed from outside. The plasma density above 1×10 10 cm −3 and uniformity below ±3.0% in diameter of 320 mm were achieved recently. The adoption of multi-pole or additional permanent magnets is under consideration to enhance the plasma confinement and uniformity.

Process considerations for critical features in high areal density thin film magnetoresistive heads: A review

Today, magnetic recording areal densities using magnetoresistive (MR) head technology are approaching 3.0 Gbit/in/sup 2/ to 4 Gbit/in/sup 2/ in products and greater than 10 Gbit/in/sup 2/ in recording demonstrations. For the first half of this decade, areal density growth for magnetic recording products has increased by 60% each year. In order to sustain this growth rate into the next ten years, much emphasis has been placed on improving the recording system with higher output sensor designs, lower noise and higher coercivity media, and more robust head disc interfaces. However, little discussion exists on the impact the 60% growth rate in areal density has on the physical dimensions and critical features of the thin film magnetoresistive head structure. This review describes the basic magnetoresistive head structure, details the basic thin film process required to fabricate the head structure, identifies the critical device features of the head, and comments on the extendibility of these features by a comparison with semiconductor device processes and geometries.

Dopant diffusion studies and free carrier lifetimes during rapid thermal processing of semiconductors

Rapid thermal processing of semiconductors involves significant photonic and subsequent thermal excitation. In the past, photonic excitation during rapid thermal annealing had been speculated to lead to significant enhancement of dopant diffusion or activation. In this work we present some experimental results indicating the absence of any such enhancement at high temperatures (∼1000–1050°C) which most often are employed during the metal-oxide–semiconductor device processing. The implanted dopant (boron, arsenic or phosphorus) movement in silicon during different rapid thermal annealing conditions was studied using secondary ion mass spectroscopy (SIMS) technique. To understand the effect of point defects in controlling the diffusion process, the concentrations of charged and neutral point defects were calculated as a function of carrier concentration using previously published defect-carrier relations. The dependence of free carrier concentration on lattice perturbation parameters such as impurities and temperature was formulated and used in calculating carrier lifetimes ( τ) in silicon. We qualitatively analyze two competing reactions, (i) the phonon release at the defect sites and (ii) the Auger electron process due to many electron interactions, to explain the apparent absence of any enhanced dopant diffusion. In our analyses, we obtain a highest free carrier lifetime of about 442 ns in the case of low dose (1e13/cm 2) implanted sample during the transient stage (700°C) of the dopant activation cycle. The corresponding smallest (∼17 fs) free carrier lifetime was obtained for the high dose implanted sample (dopants already activated) at 1000°C, the steady state part of an extended anneal cycle. Based on the detailed free carrier lifetime analyses, we suggest that any enhanced dopant activation or diffusion, at the best, may occur only at very low temperatures in the samples implanted with low doses of dopant atoms.

Nano-field effect transistor with an organic self-assembled monolayer as gate insulator

We demonstrate the realization and functioning of a hybrid (organic/silicon) nanometer-size field effect transistor (nano-FET) having a gate length of 25 nm. The gate insulator is an organic self-assembled monolayer (SAM) of alkyltrichlorosilanes (∼2 nm thick). We have used densely packed SAMs with functionalized end groups (–CH3, –CH=CH2, –COOH) that all exhibit reduced leakage current density (10−8–10−5 A/cm2). This nano-FET is free of punchthrough down to 50 nm, and shows a good field effect behavior at 25 nm. This demonstrates the compatibility of these SAMs with semiconductor device processes and their wide capability for applications in nanometer-scale electronics.

A Carbon Arc Process for Treatment of CF4 Emissions

Light perfluorocarbons, such as carbon tetrafluoride, are produced or emitted from a variety of processes, including manufacture of aluminum and processing of semiconductor devices. At the same time, the long atmospheric lifetime and high global warming potential of such compounds makes them an environmental concern. A new process for the abatement of perfluorocarbon emissions using a carbon arc plasma was investigated. In particular, the conversion of CF4 to C2F4 and higher fluorinated species, including poly(tetrafluoroethylene) (PTFE) was demonstrated. General features of the reaction chemistry are discussed, including primary reactions to form radicals and ions and secondary reactions to form C2F4 and higher compounds. The conversion efficiencies and products obtained in the reported experiments indicate potential applicability of the process for point source emission control of high global warming potential perfluorocarbons.