Effects of COVID-19 on a CMOS fabrication course: An integrated design experience.

Abstract

In the CMOS fabrication course described herein, the lecture component provides the theoretical background for semiconductor materials and integrated circuit fabrication processes. The laboratory component provides the hands‐on experience required to fabricate and electrically characterize CMOS circuits in a one‐semester format. A strong semiconductor device process design thread is achieved in the course by integrating the laboratory experience and process simulation/modeling and theoretical calculations. The risks associated with the COVID‐19 pandemic have forced significant course modifications. The lecture is switched to a remote learning format, including pre‐recorded content and weekly advanced Q&A sessions. The laboratory provides both in‐person and remote sessions. Approved social distancing and cleaning protocols are practiced in the facility for in‐person learning. Complementary remote learning resources are made available to all the students such as pre‐recorded laboratory instructions, live video‐based laboratory sessions, and web‐based supplementary information. Compared to pre‐pandemic semesters, the average students' GPA of the pandemic period has increased, attributed to larger and archived volumes of instructional material. Overall student comments related to course changes necessitated by the pandemic are mixed with both positive and negative feedback.