Schottky Barrier MOSFETs Research Articles

Dual operation modes of the Ge Schottky barrier metal–oxide–semiconductor field-effect transistor

A germanium p-channel Schottky barrier metal–oxide–semiconductor field-effect transistor (SB-MOSFET) with germanium–platinum Schottky contacts is demonstrated experimentally. The fabrication process has a low thermal budget of 450° C and requires neither intentional doping nor ion implantation. At a temperature of 4 K, the p-channel SB-MOSFET turns on at a gate voltage of −1.6 V and shows a peak mobility of 500 cm2/V s at a carrier density of 3 × 1012 cm–2. Under high drain–source bias voltages, the device operates in an unconventional mode where the current is limited by the source contact. Injection of carriers from the source contact to the germanium channel is controlled by the gate bias, which modulates the Schottky barrier capacitively. The transconductance in this mode deviates from and is significantly higher than the value expected for a conventional MOSFET with the same geometry, mobility, and capacitance. Based on four-point current–voltage measurements, we present a theoretical band diagram of the device and give a physical picture for the observed high currents and transconductances.

Optimized Nano Scaled Drain and Gate Engineered Schottky Barrier MOSFET with improved Ambipolarity and RF Characteristics

In this work, a novel structure of Schottky Barrier MOSFET (SB-MOSFET) has been presented. The proposed device consists of dual material gate and electrostatically doped drain, and the device is...

A Novel NH3 Sensing Mechanism Based on Au Pads Activated Schottky Barrier MOSFET on Silicon-on-Insulator With Extremely High Sensitivity at Room Temperature

A Novel NH₃ Sensing Mechanism Based on Au Pads Activated Schottky Barrier MOSFET on Silicon-on-Insulator With Extremely High Sensitivity at Room Temperature

Low temperature passivation of silicon surfaces for enhanced performance of Schottky-barrier MOSFET

By using a simple device architecture along with a simple process design and a low thermal-budget of a maximum of 100 °C for passivating metal/semiconductor interfaces, a Schottky barrier MOSFET device with a low subthreshold slope of 70 mV dec−1 could be developed. This device is enabled after passivation of the metal/silicon interface (found at the source/drain regions) with ultra-thin SiO x films, followed by the e-beam evaporation of high- quality aluminum and by using atomic-layer deposition for HfO2 as a gate oxide. All of these fabrication steps were designed in a sequential process so that a gate-last recipe could minimize the defect density at the aluminum/silicon and HfO2/silicon interfaces, thus preserving the Schottky barrier height and ultimately, the outstanding performance of the transistor. This device is fully integrated into silicon after standard CMOS-compatible processing, so that it could be easily adopted into front-end-of-line or even in back-end-of-line stages of an integrated circuit, where low thermal budget is required and where its functionality could be increased by developing additional and fast logic.

A Single Schottky Barrier MOSFET-Based Leaky Integrate and Fire Neuron for Neuromorphic Computing

In this paper, a Schottky Barrier MOSFET (SB-MOSFET) based on Impact Ionization mechanism is used to design a leaky integrate and fire (LIF) neuron with considerable enhancement in area, energy and cost is proposed. Using 2D calibrated simulation, we confirmed that SB-MOSFET LIF is able to replicate the neuron behavior precisely without using external circuitry. The proposed LIF neuron shows significantly lower energy per spike of 4 pJ/spike, which is lowest among the single transistor based neurons present in the literature. The recognition precision of 89.2% has been accomplished for Modified National Institute of Standards and Technology (MNIST) image. Besides this, SB-MOSFET doesn’t require any doped regions, therefore it can be fabricated with low thermal budget.

A simple sensor device for power cycle degradation sensing

A new sensor device is proposed for detection of power cycle degradation. Proposed sensor device is consisting of a Schottky-barrier MOSFET and the sensing principle is based on change of I-V characteristics by mechanical stress. Samples were fabricated by metal lift-off process and SiO2 gate insulator film deposition and the fundamental operation was evaluated by four-point bending test for mechanical stress applying. The fabricated device showed monotonically drain current change with number of stress cycles and about 5 times current change compared with initial current after 10,000 cycles of 4 N stress. Large current change by cyclic mechanical stress is attractive for a simple detection of power cycle degradation without expensive analog-circuits.

Improved Dielectrically Modulated Quad Gate Schottky Barrier MOSFET Biosensor.

A novel Schottky barrier MOSFET with quad gate and with source engineering has been proposed in this work. A high-κ dielectric is used at the source side of the channel, while SiO2 is used at the drain side of the channel. To improve the carrier mobility, a SiGe pocket region is created at the source side of the channel. Physical and electrical characteristics of the proposed device are compared with conventional double gate Schottky barrier MOSFET. It has been observed that the proposed device exhibits better performance, with a higher ION/IOFF ratio and lower subthreshold slope. The high-κ dielectric, along with the SiGe pocket region, improves tunneling probability, while aluminum, along with SiO2 at the drain side, broadens the drain/channel Schottky barrier and reduces the hole tunneling probability, resulting in a reduced OFF-state current. Further, the proposed device is used as a biosensor to detect both the charged and neutral biomolecules. Biosensors are made by creating a nanocavity in the dielectric region near the source end of the channel to capture biomolecules. Biomolecules such as streptavidin, biotin, APTES, cellulose and DNA have unique dielectric constants, which modulates the electrical parameters of the device. Different electrical parameters, viz., the electric field, surface potential and drain current, are analyzed for each biomolecule. It has been observed that drain current increases with the dielectric constant of the biomolecules. Furthermore, the sensitivity and selectivity of the proposed biosensors is better than that of conventional biosensors made using double gate Schottky barrier MOSFETs. Sensitivity is almost twice that of a conventional sensor, while selectivity is six to twelve times higher than a conventional one.

Bottom metal strip based ferroelectric Schottky Barrier MOSFET

This study develops and simulates a novel Schottky Barrier MOSFET topology that enhances device performance. The suggested device makes use of a ferroelectric material, a metal strip, and a HfO2 layer. The use of high work function metal has significantly lowered the SB thickness due to which a considerable high ION (1.72 × 10-4 A/µm) and ION-IOFF ratio (1.72 × 105) is obtained in the suggested SB-MOSFET in contrast to conventional SB-MOSFET having ION=(3.77 × 10-6) A/µm and ION/IOFF = 2.37 × 102. In contrast to the traditional SB-MOSFET, it has been noticed that the cut-off frequency, intrinsic gain, gain bandwidth product, and gain transconductance frequency product have all significantly improved.

L-Shaped Schottky Barrier MOSFET for High Performance Analog and RF Applications

L-Shaped Schottky Barrier MOSFET for High Performance Analog and RF Applications

(Invited, Digital Presentation) Approach to Neuromorphic Computing with Ferroelectric Schottky Barrier FETs

Neuromorphic computing inspired by neural network systems of the human brain enables energy efficient computing as a solution of the von Neumann bottleneck. A neural network consists of thousands or even millions of neurons which communicate with each other through connected synapses. Synapses can memorize and process the information simultaneously. The plasticity of a synapse to strengthen or weaken its activity over time make it be capable of learning and computing. Thus, artificial synapses which can emulate functionalities and the plasticity of bio-synapses form the backbone of a neuromorphic computing system.Non-volatile memories with two-terminals, like resistive random-access memory (ReRAM), phase change memory (PCM), are attractive candidates for artificial synapses. However, signal processing and learning cannot be performed simultaneously in these two-terminal synapses. FeFET, similar to a MOSFET structure using CMOS compatible HfO2 based ferroelectrics as gate oxide forms three-terminal synapses offering high endurance, good performance and high energy efficiency. In contrast to two-terminal devices, three terminal FeFET based synapses can perform processing and learning at the same time. In order to maintain the ferroelectric properties of an HfO2 based ferroelectric film, high temperature annealing should be avoided after the ferroelectric layer deposition. In this paper, we present ferroelectric NiSi2 source/drain Schottky barrier (SB) MOSFET (FE-SBFET) structure (Fig.1a), which requires neither ion implantation nor thermal activation of source/drain contacts at high temperatures.FE-SBFETs were fabricated on SOI substrates with a boron-doped (1016 B/cm-3), 55 nm thick top Si layer and a 145 nm thick buried oxide (BOX) layer. Very thin (9 nm) single crystalline NiSi2 layers which offer superior properties of uniform and stable SB contacts on Si are used at source/drain regions. A gate stack consisting of 10 nm thick Hf0.5Zr0.5O2 (HZO) layer and a 40 nm thick TiN layer are deposited by ALD and sputtering, respectively. A rapid thermal annealing at 500 °C is performed to crystallize the HZO into a ferroelectric phase before the gate patterning. The fabricated device has a channel length of 10 µm and a gate width of 10 µm. The overlap between the top gate and NiSi2 is 6 µm along the channel and 10 µm wide on each side. The ferroelectric polarization modulates both the SB at the source/drain contacts as well as the potential in the channel, thus changing the carrier injection through the SB. The Id-Vg transfer characteristics of a p-type FE-SBFET shows a clockwise hysteresis which is caused by the ferroelectric polarization switch.The excitatory post-synaptic current (EPSC), one of the typical short-term synaptic plasticity features for biologic synapses, is characterized by measuring the transient drain currents for a voltage pulse on the gate of a FE-SBFET (Fig.1b). The amplitude of the pulse VAM changes from -0.2 to -1.2 V with a fixed pulse width tpw=1 μs. We found that the EPSC peak value increases linearly with VAM. It shows a very low energy/spike consumption of 2fJ/spike at VAM=-0.2 V, demonstrating a very high energy efficiency. From the EPSC measurements with repeated gate voltage pulses paired-pulse facilitation/depression (PPF/PPD) are characterized showing an exponential decay, similar to biological synapses.The long-term synaptic plasticity of FE-SBFET synapses is characterized by a series repeated identical or non-identical pulses. The later can improve the long-term potentiation/depression (LTP/LTD) symmetry and linearity. The measurements show a large Gmax/Gmin ratio, very high endurance and small cycle-to-cycle (CTC) variation (1.06%) due to the perfect contact of NiSi2 (Fig.1c). The biological neuron-like spike-timing-dependent plasticity (STDP) is characterized for the FE-SBFET synapse. The results show an asymmetric anti-Hebbian STDP, which is one of the biological STDP functionalities (Fig.1d).In conclusion, the fabricated FE-SBFET synapse exhibits multiple synaptic functions with high endurance and small variations. The ultra-low energy/spike consumption indicates a high potential for low power neuromorphic computing applications. Acknowledgement: This work was supported by the Federal Ministry of Education and Research (BMBF, Germany) in the project NEUROTEC (16ME0398K). Figure 1

Cryogenic characteristics of UTBB SOI Schottky-Barrier MOSFETs

Schottky-Barrier (SB) MOSFETs are fabricated and characterized at room temperature (RT) and 5.4 K. The substrate bias impacts on SB MOSFETs are systematically investigated by measuring the threshold voltage Vth, subthreshold swing SS and transconductance Gm, showing the back gate has almost no effects on these parameters at 5.4 K, in contrast to the results measured at RT. Some oscillations are created in Gm curves by the quantization effect and resonant tunneling at 5.4 K. A large hysteresis is found by enhanced dynamic threshold operation at 72 K due to hot carriers and the presence of a Schottky barrier at the drain.

Silicon Nitride Interface Engineering for Fermi Level Depinning and Realization of Dopant-Free MOSFETs

Problems with doping in nanoscale devices or low temperature applications are widely known. Our approach to replace the degenerate doping in source/drain (S/D)-contacts is silicon nitride interface engineering. We measured Schottky diodes and MOSFETs with very thin silicon nitride layers in between silicon and metal. Al/SiN/p-Si diodes show Fermi level depinning with increasing SiN thickness. The diode fabricated with rapid thermal nitridation at 900 ∘C reaches the theoretical value of the Schottky barrier to the conduction band ΦSB,n=0.2 eV. As a result, the contact resistivity decreases and the ambipolar behavior can be suppressed. Schottky barrier MOSFETs with depinned S/D-contacts consisting of a thin silicon nitride layer and contact metals with different work functions are fabricated to demonstrate unipolar behavior. We presented n-type behavior with Al and p-type behavior with Co on samples which only distinguish by the contact metal. Thus, the thermally grown SiN layers are a useful method suppress Fermi level pinning and enable reconfigurable contacts by choosing an appropriate metal.

Dielectric Engineered Schottky Barrier MOSFET for Biosensor Applications: Proposal and Investigation

Dielectric Engineered Schottky Barrier MOSFET for Biosensor Applications: Proposal and Investigation

Cylindrical SOI Schottky Barrier MOSFET with High Linearity and Low Static Power for Digital and Analog Circuits Application

Non-linearity and static power consumption are major challenges in the designing of digital and analog circuits. To improve the performance of digital and analog circuits, a proper selection of MOSFET device architecture is essential. The MOSFET device architecture with low static power dissipation and high linearity results in improves overall performance at the circuit level. In this work, a detailed analysis of cylindrical Silicon-on-Insulator (SOI) Schottky Barrier (SB) MOSFET is done for analog and digital circuit applications. The analog device parameters and device non-linearity parameters for SOI SB MOSFET are extracted and compared with SB MOSFET and Dielectric Pocket (DP) SB MOSFET. The SOI SB MOSFET shows an improvement of 6.905% in output conductance (gds), 130.513% in early voltage (Vea), 240.74% in transconductance generation factor (TGF), 35.901% in transconductance frequency product (TFP), 23.529% in the gain-bandwidth product (GBWP), 25.542% in voltage gain (Av), 130.968% in gain frequency product (GFP), and 179.964% in gain transconductance frequency product (GTFP). Third-order extrapolated voltage (VIP3), third-order extrapolated power (IIP3), and extrapolated intermodulation power (IMD3) have also improved in comparison to SB MOSFET. The Atlas 3-D device simulation tool is used for numerical simulations.

Dual Metal Gate Dielectric Engineered Dopant Segregated Schottky Barrier MOSFET With Reduction in Ambipolar Current

In this paper, to solve the problem of higher ambipolar leakage current (Iambipolar) of Dielectric Engineered (DE) Dopant Segregated (DG) Schottky Barrier (SB) MOSFET (DE DS SBMOS), we have incorporated dual metal gate (DMG) in place of single metal gate for the DE DS SBMOS. The proposed device is named as DMG DE DS SBMOS. In a proposed device, the gate is consisting of dual metal having different work functions. Therefore, the gate is divided in two parts named as auxiliary gate (AG) and tunneling gate (TG). AG and TG employed near the source and drain (S/D) ends, respectively. AG is mainly used to control the on-state performance and TG for the off-state performance by modulating the SB height and width at S/D end, respectively. Simulation results show that Iambipolar of the device has been successfully suppressed by choosing appropriate work functions for AG and TG without affecting the on-state current (Ion) of the device. The proposed device combines the advantage of dual metal gate and dielectric engineering to achieve improvement in the overall performance of the device. The proposed device exhibits high Ion, low Iambipolar and low subthreshold swing (SS). The simulations study verifies the use of the proposed device for low power applications.

Investigation of Dual Metal Gate Schottky Barrier MOSFET for Suppression of Ambipolar Current

In this paper, a simulation study to suppress the ambipolar current of the Schottky Barrier (SB) MOSFET is presented. In this work, a dual metal gate device structure is used. The gate of the device is composed of two different metals. The metal used at the source side gate is used region has higher work function, while the metal used at the drain side gate region has lower work function. To perform this study, the work function of the gate metal used at the source end is kept fixed. On the other hand, to choose the appropriate metal for gate at the drain end, different work function metal has been employed. Therefore, without affecting the on-state current of the device, ambipolar current has been suppressed. In addition, the performance of the proposed device has been compared with the conventional SB MOSFET. Simulation results show that the proposed device exhibits more than two-decade reduction in ambipolar current than the conventional double gate SB MOSFET.

Performance Analyses of Planar Schottky Barrier MOSFETs with Dual Silicide Layers at Source/Drain on Bulk Substrates and Material Studies of ErSix/CoSi2/Si Stack Interface**Supported by the National Natural Science Foundation of China (No. 61474005), and the Beijing Natural Science Foundation (No. 4182025).

A dual silicide layer structure is proposed for Schottky barrier metal-oxide-semiconductor field effect transistors (MOSFETs) on bulk substrates. The source/drain regions are designed to be composed with dual stacked silicide layers, forming different barrier heights to silicon channel. Performance comparisons between the dual barrier structure and the single barrier structure are carried out with numerical simulations. It is found that the dual barrier structure has significant advantages over the single barrier structure because the drive current and leakage current of the dual barrier structure can be modulated. Furthermore, the dual barrier structure’s performance is nearly insensitive to the total silicide thickness, which can relax the fabrication requirements and even make an SOI substrate unnecessary for planar device design. The formation of ErSix/CoSi2 stacked multilayers has been proved by experiments.

Threshold Voltage Modeling of tri-Gate Schottky-Barrier (TGSB) Field-Effect-Transistors (FETs)

In this work, a threshold voltage model of Tri-Gate Schottky-Barrier (TGSB) MOSFET is presented by coupling threshold voltage models of symmetric and asymmetric double-gate Schottky-Barrier (SB) MOSFET structures giving due weight to each structure. The electrostatic potentials of double-gate SB MOSFETs are obtained using evanescent mode analysis method considering light doping in the channel region. In TGSB MOSFETs, the leakiest path in the subthreshold regime of device operation is located at the mid of the bottom of the channel region. The minimum potential of this leakiest path is considered to be the virtual cathode potential, which is subsequently used to calculate the threshold voltage of the SB MOS devices. The effects of device parameters like oxide thickness, buried oxide (BOX) thickness, channel height, width, and length, doping concentration and Schottky-Barrier height on threshold voltage have been extensively studied in this work. The proposed model results have been verified with numerical simulation results obtained from the 3-D device simulator of Sentaurus TCAD.

A Novel High Schottky Barrier Based Bilateral Gate and Assistant Gate Controlled Bidirectional Tunnel Field Effect Transistor

In this article, we propose a high Schottky barrier source/drain contacts based bilateral gate and assistant Gate controlled bidirectional tunnel field Effect transistor (HSB-BTFET). Different from Schottky barrier (SB) MOSFET which use lower Schottky barrier to produces the thermionic emission current, the proposed HSB -BTFET utilizes higher Schottky barrier to minimize the thermionic emission current and adopts bilateral gate to generate a strong band-to-band tunneling (BTBT) current which works as the conduction mechanism of the forward current. An assistant gate is introduced which efficiently blocks the reverse biased leakage current. Compared to SB MOSFET, HSB-BTFET can realize lower subthreshold swing, much smaller leakage current, higher $\text{I}_{\mathrm{ on}}-{\mathrm{ I}}_{\mathrm{ off}}$ ratio, compared to TFET, it can realize larger forward current. Besides the device symmetry, it's more compatible with MOSFET technology. The function and influence of the Schottky barrier height have been analyzed.

(Invited) Recent Progress in 4H-SiC CVD Growth for High-Voltage Power Devices

This paper reports recent progress in 4H-SiC CVD growth, aiming to obtain high-quality epilayers and bulk crystals with a high productivity for high-voltage power devices. The production of 150 mm-diameter 4H-SiC wafers has become the industry standard and the practical use of 4H-SiC unipolar devices such as Schottky barrier diodes and MOSFETS with a blocking voltage from 600 to 3,300 V started in various fields, including power conditioners for photo voltaic systems, air conditioning equipment, power supplies for IT and manufacturing industries, and inverters for electric cars and trains. Although bipolar devices such as PiN diodes and IGBTs may be more suitable for very high-voltage classes over ten kilo volts, the practical application of the bipolar devices is hindered because of the degradation phenomenon (“bipolar degradation”) in which forward on-state voltage of the devices increases after current stress applied due to the expansion of stacking faults in the crystal during current conduction. Based on the current understanding on the bipolar degradation phenomenon, basal plane dislocations (BPDs) are responsible for the nuclei of expanding single Shockley stacking faults (1SSFs) and the expansion of the 1SSFs is activated by minority carrier injection exceeding a certain level. Although epilayers with low-density BPDs (< 0.1 cm-2) were obtained by enhancing the conversion of BPDs in the substrate to threading edge dislocations (TEDs) at the beginning of epitaxial growth, the expansion of 1SSFs from the BPD segments below the conversion points was confirmed in the high current density operation [1]. This can be understood due to the injection of minority carriers into a region below the BPD-TED conversion points located near the epilayer and substrate interface or in the substrate where high-density BPDs (102 cm-2) are existing. Meanwhile, inserting a buffer layer with a short carrier lifetime between the substrate and drift epilayer has been proposed to prevent minority carrier injection into a region where BPDs remain. At this time, a thinner buffer layer is more preferable and a technique to obtain shorter carrier lifetimes compatible with the practical epitaxial growth and device fabrication processes will be promising. High nitrogen (N) doping yielding high-density free electrons has been shown as a promising method to enhance direct and Auger recombination and reduce carrier lifetimes [2, 3]. Short carrier lifetimes of 66-120 ns were obtained at RT-250 ºC for an epilayer doped with N at 5×1018 cm-3. We also attempted intentional vanadium (V) doping during epitaxial growth of a buffer layer to realize much shorter carrier lifetimes. The highly N+V-doped epilayer (N=5×1018, V=7×1014 cm-3) shows very short carrier lifetimes of ~20 ns or less at RT-250 ºC. Inserting a N- or N+V-doped buffer layer between a substrate and n- drift epilayer in the PiN diodes was confirmed to be effective to prevent the formation of 1SSFs from BPDs in the substrate. Besides continuous improvements in the quality of wafers, the strong demand to cut the cost of 4H-SiC devices from the application side may request to promote wafer productivity. Meanwhile, the development of 200 mm-diameter wafers has been demonstrated by sublimation growth in past conferences. Apart from enlarging wafer diameter, massively enhancing the growth rate or ingot length may pose the ultimate challenge in 4H-SiC bulk growth and trials featuring solution and high-temperature CVD growth methods are now underway. For high-temperature CVD growth, we attempted fast bulk crystal growth of 4H-SiC at a seed temperature of 2350-2550ºC using an H2-SiH4-C3H8-N2 gas system in a vertical CVD reactor [4]. By adjusting process parameters to enhance growth rates and improve crystal quality, fast 4H-SiC crystal growth at a growth rate exceeding 3 mm/h was achieved while maintaining the low dislocation density (threading screw dislocations: ~2.5×102 cm-2) of the seed crystal. A part of this work was supported by Council for Science, Technology and Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power electronics/Consistent R&D of next-generation SiC power electronics” (funding agency: NEDO). [1] A. Tanaka et al., J. Appl. Phys. 119, 095711 (2016), [2] T. Tawara et al., J. Appl. Phys. 120, 115101 (2016), [3] T. Tawara et al., J. Appl. Phys. 123, 025707 (2018), [4] N. Hoshino et al., J. Cryst. Growth 478, 9 (2017).