Schottky Barrier MOSFETs Research Articles

Dual metal Schottky barrier asymmetric gate stack cylindrical gate all around (DM-SB-ASMGS-CGAA) MOSFET for improved analog performance for high frequency application

In this paper dual metal Schottky barrier asymmetric gate stack cylindrical gate all around (DM-SB-ASMGS-CGAA) MOSFET is analyzed for improvement in analog performance for applications with high frequency, using ATLAS 3D device simulator. This device is compared with conventional Schottky barrier MOSFET (SB-CGAA), Schottky barrier graded stack MOSFET (SBGS-CGAA) and dual metal graded channel stack Schottky barrier MOSFET (DMSBGS-CGAA) to analyze its analog performance and applications. It is observed that DM-SB-ASMGS MOSFET shows better performance in terms of high drain current, high transconductance, gain obtained from current (CG) and gain obtained from maximum transducer power (MTPG). Early voltage and intrinsic gain are desirable for the proposed device compared to the other devices showing its capability for high-gain amplification applications. The potential and electric field results are better for the proposed device compared to the previous device architectures. The subthreshold slope obtained for DM-SB-ASMGS MOSFET is 67 (mV/decade) which is lowest among the other comparable devices and so it is highly desirable for high frequency applications. Small signal AC analysis is also carried out in order to affirm with the analog performance results. The scattering parameters (S-parameters) are taken in account and shows that it gives better performance compared to its counterparts. The reflection coefficients that are S11, S22 show better matching to ports or minimum reflection. Also the parameters S12, S21 show higher voltage gains implying that the device can be used for high gains.

Source-Drain Junction Engineering Schottky Barrier MOSFETs and their Mixed Mode Application

In this paper, a new structure for a silicon on insulator Schottky barrier MOSFET (SOI SB-MOSFET) has been proposed. The simulated device is calibrated with experimental result. Here n + pocket doping segregation in the source and drain side have been used. The simulated electrical characteristics of the proposed device With Source Extension (WSE) and With Source Drain Extension (WSDE) reveal more remarkable reduction in drain induced barrier tunneling (DIBT), high Ion/Ioff and low Subthreshold swing(SS) than conventional device. Furthermore, the effect of varying temperature has been investigated on subthreshold swing for various oxide thickness (Tox) and silicon film thickness (TSi). Moreover, proposed SB-MOSFETs have been used in the inverter circuit, exhibit a high gain (˷12) and Noise Margin (NMH = 0.4 and NML = 0.46).

Two-Dimensional Potential and Threshold Voltage Modeling of Work Function Engineered Double Gate High-k Gate Stack Schottky Barrier MOSFET

Following the ongoing research trend towards the development of nonconventional metal–oxide–semiconductor field-effect transistor (MOSFET) structures to reduce the detrimental influence of various short-channel effects associated with the continual miniaturization of device dimensions through several technology nodes, we have explored a Schottky barrier symmetric double gate (DG) MOSFET incorporating the concepts of gate engineering and dielectric engineering, viz. a work function engineered double gate Schottky barrier MOSFET with high-k gate stack. The study primarily addresses issues related to the source–channel and drain–channel junctions of highly scaled devices by considering metallic source and drain regions to benefit from the barrier height lowering at the metal–semiconductor junctions along with reduced contact resistances, which improves the performance of the proposed device in terms of surface potential, electric field, threshold voltage roll-off, drain-induced barrier lowering, etc. The results obtained from detailed two-dimensional threshold voltage modeling are found to be in excellent agreement with the simulation results, validating the presented analytical model.

Modeling and Analysis of a Front High-k gate stack Dual-Material Tri-gate Schottky Barrier Silicon-on-Insulator MOSFET with a Dual-Material Bottom Gate

The present work centralizes the analytical modeling of a novel structure namely front high-k gate stack Dual-Material Tri-gate Silicon-on-insulator Schottky barrier MOSFET with a dual material bottom gate along with an emphasis on its response towards the various SCEs. 3-D Poisson’s equation along with proper boundary conditions has been solved considering the popular parabolic potential approximation. Different device features like surface potential, threshold voltage, electric field has been studied. Also the device immunity towards the several Short channel effects like drain-induced barrier lowering, threshold voltage roll-off, hot carrier effects are investigated minutely. The analytical results obtained have been verified using simulation results obtained from ATLAS.

Enhancing the Thermal Stability of GaSb Schottky-Barrier MOSFET With Pt Source/Drain

In this study, a Pt/GaSb Schottky diode with impressive rectifying behavior is used for the first time in the fabrication of a GaSb p-channel Schottky-barrier metal–oxide–semiconductor field-effect transistor (MOSFET). A gate-last integration scheme was employed to fabricate the MOSFET. Compared with a MOSFET with a Ni-alloy source and drain (S/D), the MOSFET with a Pt-alloy S/D can endure higher thermal stress during atomic layer deposition at 250 °C for 1 h without significant junction degradation. This high endurance to thermal stress is because Pt alloy has a lower reactivity to GaSb and a higher crystallization temperature. As a result, a record high ON/OFF ratio of $3\times 10^{ {4}}$ is reported for the GaSb Schottky-barrier MOSFET; an effective hole mobility of approximately 82 cm2V−1s−1 is achieved.

Non-destructive Detection of Screw Dislocations and the Corresponding Defects Nucleated from Them During SiC Epitaxial Growth and Their Effect on Device Characteristics

In high-volume manufacturing of SiC power devices like Schottky barrier diodes and MOSFETs, especially with the high demands of high reliability applications like the automotive market, the issue of reliability needs to be tackled from multiple angles. It becomes important to isolate and eliminate failure mechanisms at the source rather than just rely on electrical tests. As we enter volume production on 150-mm substrates, an added layer of reliability and improved yield can be added if potential sources of defects are identified and removed. In this work, we present the non-destructive detection of a subset of screw dislocations in N+ doped substrates, trace the preferential nucleation of V-type epitaxial defects and stacking faults from these screw dislocations, and study their electrical effects on Schottky diodes. This enables the screening of highly defective substrates even before committing them to epitaxial growth.

Novel attributes of bandstructure effect on the performance of germanium Schottky barrier MOSFET

A detailed study of the bandstructure effect on the performance of a double-gate germanium Schottky barrier MOSFET (Ge-SBFET) is investigated. An accurate calculation of the thickness-dependent 2D bandstructure is employed within a 20 orbital sp3d5s* tight-binding formalism, and the quantum transport of the carriers is elucidated based on the non-equilibrium Green’s function formalism. Quantum confinement considerably changes the bandstructure profile of the Ge-SBFET and causes the energy difference of the valleys to rearrange. For a channel thickness of about 1.5 nm, the two-fold X2 type valleys with major axes at the point form a subband with minimum energy, and the energy split is reduced to 13 meV, which compensates for the lack of density of states in the nanoscale regime. Moreover, the strong transverse confinement of the ultra-thin body Ge-SBFET increases the effective Schottky barrier height and a parabolic potential profile with discrete resonant states is formed along the current transport direction, mainly at low drain voltages. Resonant tunnelling creates oscillations in the transfer characteristic, especially at low temperatures and at a reduced value of drain voltages. The impact of the physical and structural parameters, which may affect the resonant tunnelling in a Ge-SBFET, is thoroughly analysed. The results in this paper pave the way towards elucidating the applications of nanoscale Ge-SBFETs.

Tuning of Schottky Barrier Height at NiSi/Si Contact by Combining Dual Implantation of Boron and Aluminum and Microwave Annealing.

Dopant-segregated source/drain contacts in a p-channel Schottky-barrier metal-oxide semiconductor field-effect transistor (SB-MOSFET) require further hole Schottky barrier height (SBH) regulation toward sub-0.1 eV levels to improve their competitiveness with conventional field-effect transistors. Because of the solubility limits of dopants in silicon, the requirements for effective hole SBH reduction with dopant segregation cannot be satisfied using mono-implantation. In this study, we demonstrate a potential solution for further SBH tuning by implementing the dual implantation of boron (B) and aluminum (Al) in combination with microwave annealing (MWA). By using such a method, not only has the lowest hole SBH ever with 0.07 eV in NiSi/n-Si contacts been realized, but also the annealing duration of MWA was sharply reduced to 60 s. Moreover, we investigated the SBH tuning mechanisms of the dual-implanted diodes with microwave annealing, including the dopant segregation, activation effect, and dual-barrier tuning effect of Al. With the selection of appropriate implantation conditions, the dual implantation of B and Al combined with the MWA technique shows promise for the fabrication of future p-channel SB-MOSFETs with a lower thermal budget.

A physics‐based threshold voltage model for hetero‐dielectric dual material gate Schottky barrier MOSFET

AbstractThis paper presents the analytical model of threshold voltage for hetero‐dielectric dual material gate Schottky barrier (SB) metal oxide semiconductor field effect transistor (MOSFET). The threshold voltage model is derived on the basis of the surface potential model. The threshold voltage is extracted using transconductance change method. The two‐dimensional surface potential, electric field, and threshold voltage model for the hetero‐dielectric dual material gate SB‐MOSFET are developed using 2‐D Poisson's equation, which satisfies the boundary conditions. Moreover, the model precisely depict the impact of hetero‐gate dielectric and gate oxide thickness on the surface potential, and threshold voltage of the hetero‐dielectric dual material gate SB and compared with single material gate SB‐MOSFET. Finally, a good agreement between the model results and numerical simulated results is achieved.

Electrostatically Doped DSL Schottky Barrier MOSFET on SOI for Low Power Applications

In this paper, we propose and simulate a novel Schottky barrier MOSFET (SB-MOSFET) with improved performance in comparison to the conventional SB-MOSFET. The proposed device employs charge plasma/electrostatic doping-based dopant segregation layers (DSLs) by using metal extensions (Hafnium) at the source and drain top and bottom edges. The metal hafnium induces charge plasma and hence realizes DSLs adjacent to source and drain regions. These charge plasma DSLs reduce the tunneling width and hence enhances the performance of the proposed device. The proposed electrostatically doped DSL-based SB-MOSFET has all the advantages of the conventional SB-MOSFET and it outperforms the state of the art doped DSL-based MOSFET. A two-dimensional calibrated simulation study has shown that the ON current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ), I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio, subthreshold-swing and cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of the proposed device have been increased by ~420 times, ~1000 times, 14.5%, and 290 times in comparison to conventional SB-MOSFET, respectively. The transient analyses have shown that a reduction by 16 times in ON delay and 6 times in OFF delay in the proposed device-based inverter in comparison to the conventional SB-MOSFET-based inverter.

Charge plasma based source/drain engineered Schottky Barrier MOSFET: Ambipolar suppression and improvement of the RF performance

This paper reports a novel device structure for charge plasma based Schottky Barrier (SB) MOSFET on ultrathin SOI to suppress the ambipolar leakage current and improvement of the radio frequency (RF) performance. In the proposed device, we employ dual material for the source and drain formation. Therefore, source/drain is divided into two parts as main source/drain and source/drain extension. Erbium silicide (ErSi1.7) is used as main source/drain material and Hafnium metal is used as source/drain extension material. The source extension induces the electron plasma in the ultrathin SOI body resulting reduction of SB width at the source side. Similarly, drain extension also induces the electron plasma at the drain side. This significantly increases the SB width due to increased depletion at the drain end. As a result, the ambipolar leakage current can be suppressed. In addition, drain extension also reduces the parasitic capacitances of the proposed device to improve the RF performance. The optimization of length and work function of metal used in the drain extension is performed to achieve improvement in device performance. Moreover, the proposed device makes fabrication simpler, requires low thermal budget and free from random dopant fluctuations.

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported, to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. This novel structure offers low barrier height at the source and offers high ON-state current. The ION/IOFF of ISE-CGAA-SB-MOSFET increases by 1177 times and offers steeper subthreshold slope (~60 mV/decade). However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate, dual metal gate, single metal gate with ISE, and dual metal gate with ISE has been presented. The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design. The numerical simulation is performed using the ATLAS-3D device simulator.

Transport Properties and Device Prospects of Ultrathin Black Phosphorus on Hexagonal Boron Nitride

Black phosphorus (BP) has re-emerged as a promising layered material with significant potential for future nanoelectronic applications. Several recent studies have demonstrated an improvement in the transport properties of BP channels when insulated from SiO2 substrates using hexagonal boron nitride (hBN) (or when fully encapsulated). This improvement is typically characterized using extractions of mobility based on the empirical relationship between conductivity and carrier density. However, this does not provide insight into the transport mechanisms, nor it allows accounting for differences in intrinsic (e.g., bandgap and effective mass) and extrinsic (e.g., trap density/distribution and Schottky barrier heights) properties in the analysis. Here, we present a modeling approach for Schottky-barrier MOSFETs with low-dimensional channel materials based on the Landauer theory. To analyze transport improvement in hBN-insulated BP channels we fabricate and measure BP Schottky-barrier-MOSFETs with and without the hBN insulating layer. Our analysis demonstrates ~80% improvement in low-field effective channel mobility and an (energy averaged) scattering mean free path that is >5 times larger for BP devices with an underlying hBN layer compared to devices with BP directly on SiO2.

Design and Investigation of Dielectric Engineered Dopant Segregated Schottky Barrier MOSFET With NiSi Source/Drain

In this paper, to solve an important issue of low ON-state current in the nickel silicide (NiSi) metal source/drain Schottky barrier (SB) MOSFET (SBMOS), we have reported a novel dielectric engineered (DE) dopant segregated (DS) SBMOS structure using gate dielectric engineering. In a proposed device, we employ two different gate dielectric materials. The high-k gate dielectric is used at the source side and low-k gate dielectric at the drain side. Beneath the high-k gate dielectric, electron accumulation increases due to large gate dielectric capacitance density. As a result, reduction in depletion of source side dopant segregation layer further decreases the SB tunneling width for the electron injection. Consequently, improvement in ON-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) is obtained. In addition, the low-k gate dielectric and drain side dopant segregation layer increases the effective SB height and tunneling width for the hole injection. Thus, the OFF-state current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) is suppressed. The optimization of proposed device has been performed by modulating the length of high-k and the low-k gate dielectric. In addition, we have compared the performance of the proposed device in terms of ON to OFF current ratio $({I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}})$ , subthreshold swing (SS), transconductance $({g}_{ {m}})$ , transconductance generation factor $({g}_{ {m}}/{I}_{ {D}})$ , cut-off frequency $({f}_{ {T}})$ , and gain-bandwidth product $({f}_{ {A}})$ to the SBMOS, DS SBMOS, and DS SBMOS with the full high-k gate dielectric. Moreover, we have proposed the possible process flow for the DE DS SBMOS fabrication.

On the Physical Behavior of Cryogenic IV and III–V Schottky Barrier MOSFET Devices

The physical influence of temperature down to the cryogenic regime is analyzed in a comprehensive study and the comparison of IV and III-V Schottky barrier (SB) double-gate MOSFETs. The exploration is done using the Synopsys TCAD Sentaurus device simulator and first benchmarked with experimental data. The important device physics of both SB-MOSFETs and conventional MOSFETs are reviewed. The impact of temperature on device performance down to the liquid-nitrogen regime is then explored. We find reduced drive currents in SB-MOSFETs fabricated on small effective mass materials and that SB lowering can significantly improve SB-MOSFETs, especially at low temperatures.

Experimental I–V and C–V Analysis of Schottky-Barrier Metal-Oxide-Semiconductor Field Effect Transistors with Epitaxial NiSi2 Contacts and Dopant Segregation**Supported by the National Natural Science Foundation of China under Grant No 61674161, and the Open Project of State Key Laboratory of Functional Materials for Informatics.

We present an experimental analysis of Schottky-barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) fabricated on ultrathin body silicon-on-insulator substrates with a steep junction by the dopant implantation into the silicide process. The subthreshold swing of such SB-MOSFETs reaches 69 mV/dec. Emphasis is placed on the capacitance-voltage analysis of p-type SB-MOSFETs. According to the measurements of gate-to-source capacitance with respect to at various , we find that a maximum occurs at the accumulation regime due to the most imbalanced charge distribution along the channel. At each peak, the difference between and is equal to the Schottky barrier height (SBH) for NiSi2 on highly doped silicon, which indicates that the critical condition of channel pinching off is related with SBH for source/drain on channel. The SBH for NiSi2 on highly doped silicon can affect the pinch-off voltage and the saturation current of SB-MOSFETs.

2-D analytical modeling for electrostatic potential and threshold voltage of a dual work function gate Schottky barrier MOSFET

A two-dimensional analytical model for the surface potential and threshold voltage of a dual work function Schottky barrier (SB) MOSFET is presented. The developed model considers the effects of the varying gate metal work function, gate and drain voltages, and different doping concentrations, gate dielectric permittivity, and silicon thickness. For solving the electrostatic potential of the SB-MOSFET by using Poisson’s equation with appropriate boundary conditions, parabolic approximation has been considered. The proposed device has also incorporated the effect of barrier height lowering at the metal/semiconductor contacts. The results of our modeled surface potential and the threshold voltage, match with technology computer aided design simulations.

2D analytical model for surface potential based electric field and impact of wok function in DMG SB MOSFET

In this paper an analytical surface potential model of a dual material gate (DMG) Schottky Barrier (SB) metal-oxide-semiconductor field effect transistor (MOSFET) is explored. The surface potential model is established by using two-dimensional solution of Poisson's equation, with essential boundary conditions near the drain and source ends. The proposed device has metal-semiconductor (Schottky) junction instead of p-n junction. In the DMG structure the effect of work function, drain to source voltage, gate to source voltage on the surface potential are observed. Furthermore, the simulation results of proposed DMG-SB-MOSFET shows good immunity to short channel effects(SCE) and is assessed by considering the drain-induced barrier lowering(DIBL) and compared with equivalent single material gate (SMG) SB- MOSFET. Moreover, the DMG and SMG SB-MOSFET are compared in terms of ambipolar behavior, ON-state and OFF-state current of the device. The developed analytical model for surface potential along the channel length are in close agreement with the Silvaco Technology Computer Aided Design device simulator data.

Current Modeling for Accumulation Mode GaN Schottky Barrier MOSFET for Integrated UV Sensors

Current Modeling for Accumulation Mode GaN Schottky Barrier MOSFET for Integrated UV Sensors

(Invited) Progress in Buried Grid Technology for Improvements in on-Resistance of High Voltage SiC Devices

Silicon Carbide (SiC) is regarded as the material of choice for high voltage (>1kV) power devices due to its material properties, mature fabrication technology, and availability of 150mm diameter wafer material. SiC power devices like Schottky barrier diodes (SBDs) and MOSFETs with voltage ratings of 1700V and current handling capabilities of 50A and more are commercially available from several vendors. Commercial SiC SBDs are based on the merged p-n junction and Schottky (MPS) concept or the junction barrier controlled Schottky (JBS) concept. Commercial MOSFETs utilize the VDMOS concept having a vertical device design with lateral channel and the UMOS concept with vertical channel at trench sidewalls. Common for these device concepts is that the electric field at device areas like Schottky contacts and MOS interfaces is relatively high and limits often the device performance. This leads to that the full potential of SiC devices cannot be realized. For example, in planar surface p-grid JBS diode structures the protection of the Schottky areas from high electric field is not sufficient and result in high leakage currents limiting the SOA in terms of junction and operation temperature. In addition, the edge termination is realized at the top surface of the SiC material and has to be carefully designed to not exceed the limitations of passivation and packaging materials. Buried grid technology is suggested to decrease the electric field at field sensitive device areas and to move areas of high electric field into the SiC bulk. It was demonstrated for SiC JBS diodes that buried grid technology gives more than three orders of magnitude lower leakage currents even at high temperature operation due to the superior shielding effect. The drawback is that the introduction of the buried grid increases the total resistance and therefore increases the forward voltage drop at rated current and the conduction losses. In this paper, we review our work on improving the on-state characteristics of buried grid SiC devices. The work is mainly done for buried grid JBS-diodes (BG-JBS), but can be applied also to buried grid MOSFETs (BG-MOSFET). For the BG-SiC devices, a p-grid is fabricated either by aluminum implantation followed by high temperature anneal or trench etching with subsequent epitaxial re-growth and planarization to fill up etched trenches with p-type material. As a final step, the p-grid is buried by another re-growth step of a thin n-layer. The epitaxial grid approach is done with Ascatron’s 3D-SiC core technology based on embedded epitaxial growth techniques, replacing high dose ion implantation at elevated temperatures and high temperature anneal by epitaxial growth in trenches. For cost-effective fabrication, this process should be performed in multi-wafer reactors. For devices with blocking capability of up to 1700V, we typically employ floating ring type edge termination formed simultaneously with the active area p-grid. For higher voltages than 1700V we suggest to use a JTE type edge termination formed by ion implantation in the same layer as the p-grid. Hence, the edge termination is also buried in the SiC bulk. By carefully designing the drift and re-growth layers as well as the epitaxial or implanted p-grid, the fabrication process can be optimized in terms of trade-off between current handling capability in forward and blocking behavior and leakage current in reverse. In addition, the size and spacing of the p-areas are critical parameters to optimize the BG-SiC device performance to realize maximum current handling capability at forward voltage similar or below surface grid devices and minimum leakage current especially for high temperature operation. To reduce the forward voltage, we employed relatively high n-doping in the channel regions between the p-islands and optimized the drift and re-grown top layer doping. Due to the superior material quality, epitaxial grown BG-structures result in increased bipolar injection at high current densities and thus give improved surge current capabilities. In addition, epitaxial p-n junctions show lower leakage currents than implanted ones.