Scan-based Built-in Self-test Research Articles

Low Power Scan-based Built-in Self-test Based on True Random Number Generator Using Multistage Feedback Ring Oscillator

Low Power Scan-based Built-in Self-test Based on True Random Number Generator Using Multistage Feedback Ring Oscillator

A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips

High power dissipation in scan-based logic built-in self-test (LBIST) is a crucial issue that can cause over-testing, reliability degradation, chip damage, and so on. While many sophisticated approaches to low-power testing have been proposed in the past, it remains a serious problem to control the test power of LBIST to a predetermined appropriate level that matches the power requirements of the circuit-under-test. This paper proposes a novel power-control method for LBIST that can control the scan-shift power to an arbitrary level. The proposed method modifies pseudo-random patterns generated by an embedded test pattern generator (TPG) so that the modified patterns have the specific toggle rate without sacrificing fault coverage and test time. In order to evaluate the effectiveness of the proposed method, this paper shows not only simulation-based experimental results but also measurement results on test element group (TEG) chips.

Low Cost Test Pattern Generation in Scan-Based BIST Schemes

This paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes. Our method generates broadcast-based multiple single input change (BMSIC) vectors to fill more scan chains. The proposed algorithm, BMSIC-TPG, is based on our previous work multiple single-input change (MSIC)-TPG. The broadcast circuit expends MSIC vectors, so that the hardware overhead of the test pattern generation circuit is reduced. Simulation results with ISCAS’89 benchmarks and a comparison with the MSIC-TPG circuit show that the proposed BMSIC-TPG reduces the circuit hardware overhead about 50% with ensuring of low power consumption and high fault coverage.

Detection of Stuck Open and Short Fault in SRAM Based System

A novel scan-based Built-In Self-Test (BIST) architecture is designed with Low-Power (LP) for weighted pseudorandom test pattern generation (WPTPG) and reseeding, which is easy for the pseudorandom testing and deterministic BIST. The pseudorandom testing stage is designed by disabling a section of scan chains and in the deterministic BIST stage, the design-for-testability architecture is reorganize slightly while the linear-feedback shift register is kept short. The proposed technique of a BIST design for fault detection and fault diagnosis of Static-RAM (SRAM) based Field Programmable Gate Array (FPGAs) can detect the interconnect resources in the Configurable Logic Blocks (CLBs). The test pattern generator and output response analyzer are configured by CLBs in FPGAs. The testing procedure undergoes three major test blocks. They are Test Pattern Generator (TPG), Output Response Analyzer (ORA) and Block Under Test (BUT) in each test block. The stuck open and short faults are detected using SRAM based FPGA are observed in this paper.

New Approaches for Power Binning of High Performance Microprocessors

The significant process parameter variations occurring during fabrication of high performance sequential circuits, such as microprocessors, are posing relevant uncertainties on the power that such circuits will consume in the field, while executing workloads typical for the diverse products they are oriented to (e.g., cellular phones, notebooks, servers, etc). On the other hand, different kinds of products have different constraints on the maximal power that could be consumed during the execution of typical workloads, due to diverse needs in terms of charge autonomy, heat dissipation, etc. Consequently, the power that will be consumed by microprocessors during the execution of typical workloads in the field needs to be accurately characterized at the end of fabrication. Such a power consumption characterization (hereinafter referred to as “power binning”), will enable to classify microprocessors in “power bins”, each one containing microprocessors suitable for different kinds of products, thus enabling to introduce them all into the market for different kinds of products. Based on these considerations, in this paper we propose an approach to characterize accurately at the end of fabrication, and at low-cost (in terms of characterization time), the power that microprocessors will consume in the in-field during the execution of workloads typical for different kinds of products. Our approach exploits scan-based Logic Built-In Self-Test (LBIST) to apply to microprocessors’ sequential blocks test vectors that induce on their internal nodes an activity factor (AF) similar to that experienced during the in-field execution of workloads typical for different kinds of products, thus enabling to perform power binning by simply measuring their consumed power. Our approach enables to scale the AF from 0 percent up to 97.6 percent (on average for the considered benchmark circuits) compared to conventional LBIST, with a granularity of the 2 percent, thus enabling to emulate accurately the AF induced by workloads typical of a wide range of products. We propose a hardware implementation for our approach requiring a limited area overhead (lower than 3 percent) over conventional LBIST.

Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding

A new low-power (LP) scan-based built-in self-test (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministic BIST. During the pseudorandom testing phase, an LP weighted random test pattern generation scheme is proposed by disabling a part of scan chains. During the deterministic BIST phase, the design-for-testability architecture is modified slightly while the linear-feedback shift register is kept short. In both the cases, only a small number of scan chains are activated in a single cycle. Sufficient experimental results are presented to demonstrate the performance of the proposed LP BIST approach.

MULTI-DEGREE SMOOTHER FOR LOW POWER TESTABLE DIGITAL SYSTEM DESIGN USING BS-LFSR AND SCAN-CHAIN ORDERING TECHNIQUES

Testing of digital VLSI circuits entails many challenges as a consequence of rapid growth of semiconductor manufacturing technology and the unprecedented levels of design complexity and the gigahertz range of operating frequencies. These challenges include keeping the average and peak power dissipation and test application time within acceptable limits. This dissertation proposes techniques to addresses these challenges during test. The first proposed technique, called bit-swapping LFSR (BS-LFSR), uses new observations concerning the output sequence of an LFSR to design a low-transition test-pattern-generator (TPG) for test-per-clock built-in self-test (BIST) to achieve reduction in the overall switching activity in the circuit-under-test (CUT). The obtained results show up to 28% power reduction for the proposed design, and up-to 63% when it is combined with another established technique. The proposed BS-LFSR is then extended for use in test-per-scantest vectors show up to 60%reduction in average power consumption. The BS-LFSR is then extended further to act as a multi-degree smoother for test patterns generated by conventional LFSRs before applying them to the CUT. Experimental results show up to 55% reduction in average power. Another technique that aims to reduce peak power in scan-based BIST is presented. The new technique uses a two-phase scan-chain ordering algorithm to reduce average and peak power in scan and capture cycles. Experimental results show up to 65% and 55% reduction in average and peak power, respectively. Finally, a technique that aims to significantly increase the fault coverage in test-Per scan BIST, while keeping the test-application time short, is proposed. The results obtained show a significant improvement in fault coverage and test application time compared with other techniques.

Strategies and Techniques for Optimizing Power in BIST: A Review

Power dissipation is a challenging problem in current VLSI designs. In general the power consumption of device is more in the testing mode than in the normal system operation. Built in self test (BIST) and scan-based BIST are the techniques used for testing and detecting the faulty components in the VLSI circuit. Linear Feedback Shift Register (LFSR) in BIST generates pseudo-random patterns for detecting the faults, increasing the power consumption during testing, boosting the need to add power optimizations to BIST pattern generators. This paper identifies the different techniques to modify the BIST architecture thereby finding an optimal choice to reduce power consumption without compromising upon fault coverage. General Terms Power optimization, IP cores.

Low Transition Test Pattern Generator Architecture for Built-in-Self-Test

Problem statement: In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by linear feedback shift registers. This normally requires more number of test patterns for testing the architectures which need long test time. Approach: This study presents a novel test pattern generation technique called Low-Transition Generalized Linear Feedback Shift Register (LT-GLFSR) with bipartite (half fixed) and bit insertion (either 0 or 1) techniques. Intermediate patterns (by bipartite and bit (either 0 or 1) insertion technique) inserted in between consecutive test patterns generated by GLFSR which is enabled by a non overlapping clock scheme. This process is performed by finite state machine generate sequence of control signals. Low-Transition Generalized Linear Feedback Shift Registers (LT-GLFSR), are used in a circuit under test to reduce the average and peak power during transitions. LT-GLFSR patterns high degree of randomness and correlation between consecutive patterns. LT-GLFSR does not depend on circuit under test and hence it is used for both BIST and scan-based BIST architectures. Results and Conclusion: Simulation results prove that this technique has reduction in power consumption and high fault coverage with minimum number of test patterns. The results also show that it reduces the peak and average power consumption during test for ISCAS’89 bench mark circuits.

Low Transition-Generalized Linear Feedback Shift Register Based Test Pattern Generator Architecture for Built-in-Self-Test

Problem statement: In Built-In Self-Test (BIST), test patterns are ge nerated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by Linear Feedback Shift Registers. This nor mally requires more number of test patterns for testing the architectures which need long test time . Approach: This study presents a novel test pattern generation technique called Low-Transition Generali zed Linear Feedback Shift Register (LT-GLFSR) and it was also called Bipartite GLFSR. Intermediat e pattern (Bipartite technique) inserted in between consecutive test patterns generated by GLFSR was called LT-GLFSR technique which was enabled by a non overlapping clock scheme. Low-transition generalized linear feedback shift registers (LT-GLFSR), was used in a circuit under test to reduce the aver age and peak power during transitions. LT-GLFSR pattern generator would generate patterns with high er degree of randomness and high correlation between consecutive patterns would have efficient area impl ementation. LT-GLFSR did not depend on circuit under test and hence it could be used for both BIST and scan-based BIST architectures. Results/Conclusion: Simulation results show that this technique has re duction in power consumption and high fault coverage with minimum number of test patterns. The results also show that it reduces th e peak and average power consumption during test for ISCAS'89 bench mark circuits.

A low power test pattern generation for built-in self-test based circuits

A low-power test pattern generation, named the low switching activity test pattern generation (LSA-TPG), is proposed to reduce the power dissipation of built-in self-test (BIST)-based circuits during test. A single input changing (SIC) test pattern is generated by a counter and a Gray encoder which is called the SICG (single input changing generator). The built-in test vectors are generated by the SIC patterns which are exclusive-ORed with seeds generated by the modified linear feedback shift register (LFSR). All the test vectors are SIC patterns during the 2m test clock period; thus the switching activities of the test vectors are greatly reduced in test mode without compromising fault coverage. The proposed structure has the advantages of low test power and low hardware overhead. LSA-TPG is independent of circuit under test (CUT) and flexible enough to be used in both BIST and scan-based BIST architectures. The proposed architecture increases the correlation among the test patterns with negligible impact on test length. Experiments conducted on ISCAS'89 benchmark circuits demonstrate that the proposed scheme gives better fault coverage with a large reduction in test power dissipation.

Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains

This paper presents a new at-speed logic built-in self-test (BIST) architecture supporting two launch-on-capture schemes, namely aligned double-capture and staggered double-capture, for testing multi-frequency synchronous and asynchronous clock domains in a scan-based BIST design. The proposed architecture also includes BIST debug and diagnosis circuitry to help locate BIST failures. The aligned scheme detects and allows diagnosis of structural and delay faults among all synchronous clock domains, whereas the staggered scheme detects and allows diagnosis of structural and delay faults among all asynchronous clock domains. Both schemes solve the long-standing problem of using the conventional one-hot scheme, which requires testing each clock domain one at a time, or the simultaneous scheme, which requires adding isolation logic to normal functional paths across interacting clock domains. Physical implementation is easily achieved by the proposed solution due to the use of a slow-speed, global scan enable signal and reduced timing-critical design requirements. Application results for industrial designs demonstrate the effectiveness of the proposed architecture.

A BIST TPG for Low Power Dissipation and High Fault Coverage

In This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed BIST is comprised of two TPGs: LT-RTPG and 3- weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT-RTPG patterns are applied. The proposed BIST TPG does not require modification of mission logics, which can lead to performance degradation. Experimental results for ISCAS’89 benchmark circuits demonstrate that the proposed BIST can significantly reduce switching activity during BIST while achieving 100% fault coverage for all ISCAS’89 benchmark circuits. Larger reduction in switching activity is achieved in large circuits. Experimental results also show that the proposed BIST can be implemented with low area overhead.

Scan BIST with biased scan test signals

The conventional test-per-scan built-in self-test (BIST) scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flipflops are shifted out while shifting in the next test vector like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the test signals of the scan chains. Different biased random values are assigned to the test signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly, and most circuits can obtain complete fault coverage or very close to complete fault coverage.

A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST

We present a new scan-based built-in self-test (BIST) technique, which is based on weighted scan-enable signals and a reconfigurable scan-forest architecture. A testability measure is proposed to guide test pattern generation and produce patterns with few care bits. This approach can effectively reduce the amount of test data that needs to be stored on-chip. The proposed BIST method relies on the pseudorandom and deterministic phases. The scan-forest architecture is configured as a single scan tree for deterministic test vector application in the second phase. It is found that a linear feedback shift register, with size equal to the maximum number of the care bits in the deterministic patterns for the random-resistant faults, is sufficient to encode deterministic vectors for the benchmark circuits. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method for single stuck-at faults. In addition, experimental results show that the patterns applied to the circuit under test provide more n-detection than those applied by a traditional scan-chain architecture with a single test session.

Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST

The conventional test-per-scan built-in self-test (BIST) scheme needs a number of shift cycles followed by one capture cycle. Fault effects received by the scan flip-flops are shifted out while shifting in the next test vector, like scan testing. Unlike deterministic testing, it is unnecessary to apply a complete test vector to the scan chains. A new scan-based BIST scheme is proposed by properly controlling the scan enable signals of the scan chains. Different weighted values are assigned to the scan enable signals of scan flip-flops in separate scan chains. Capture cycles can be inserted at any clock cycle if necessary. A new testability estimation procedure according to the proposed testing scheme is presented. A greedy procedure is proposed to select a weight for each scan chain. Experimental results show that the proposed method can improve test effectiveness of scan-based BIST greatly and most circuits can obtain complete fault coverage or very close to complete fault coverage.

A BIST TPG for Low Power Dissipation and High Fault Coverage

This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed BIST is comprised of two TPGs: LT-RTPG and 3-weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT-RTPG patterns are applied. The proposed BIST TPG does not require modification of mission logics, which can lead to performance degradation. Experimental results for ISCAS'89 benchmark circuits demonstrate that the proposed BIST can significantly reduce switching activity during BIST while achieving 100% fault coverage for all ISCAS'89 benchmark circuits. Larger reduction in switching activity is achieved in large circuits. Experimental results also show that the proposed BIST can be implemented with low area overhead.

Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size

The authors propose a low-power testing methodology for the scan-based built-in self-test. This approach combines a low-power test pattern generator (TPG) with scan-chain reordering to achieve low-power testing without losing fault coverage. Three main issues are addressed. First, a smoother is included in the TPG to reduce the average power consumption. However, the fault coverage may be adversely affected by the smoother; hence, a cluster-based scan-chain reordering is employed to remedy this problem. If a very-large power reduction is necessary, the fault-coverage drop can become significant. This can be addressed by reseeding. The second topic of this paper is to give a detailed analysis on the optimal cluster size to minimize the scan-chain length. Finally, a fast and efficient algorithm is developed for scan-chain reorder in order to improve the fault coverage. The reordering algorithm is very efficient in terms of computation time, and the routing length of the reordered scan chain is comparable to or smaller than the result given by commercial tools. Experimental results show that the proposed method provides a significant and consistent reduction in the average test power, and the fault coverage is similar to previous methods with the same test lengths

Improving test effectiveness of scan-based BIST by scan chain partitioning

Test effectiveness of a test-per-scan built-in self-test (BIST) scheme is highly dependent on the length and number of scan chains. Fewer cycles are used to capture test responses when the length of the scan chains increases and the total number of clock cycles is fixed. Another important feature of the test-per-scan BIST scheme is that test responses of the circuit at the inputs of the scan flip-flops are not observable during the shift cycles. A new scan architecture is proposed to make a scan-based circuit more observable. The scan chain is partitioned into multiple segments. Multiple capture cycles are inserted to receive test responses during the shift cycles compared to the test-per-scan test scheme. Unlike other BIST schemes using multiple capture cycles after the shift cycles, our method inserts multiple capture cycles inside the shift cycles, but not after the shift cycles. Unlike the previous method that drives multiple scan segments by a single scan-in signal, the proposed method uses a new architecture to control all scan segments by different signals. Sufficient experimental results are presented to demonstrate the effectiveness of the method.

Multiphase BIST: A New Reseeding Technique for High Test-Data Compression

In this paper, a new reseeding architecture for scan-based built-in self-test (BIST), which uses a linear feedback shift register (LFSR) as test pattern generator, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan chain of the circuit under test in different test phases. The LFSR generates the same state sequence in all phases, keeping that way the implementation cost low. A seed-selection algorithm is furthermore presented that, taking advantage of the multiphase architecture, manages to significantly reduce the number of the required seeds for achieving complete (100%) fault coverage. The proposed technique can be used either in a full BIST implementation or in a test-resource partitioning scenario, since the test-data storage requirements on the tester are very low. When a full BIST implementation is preferable, the multiphase architecture can also be combined with a dynamic reseeding scheme that uses combinational logic instead of a ROM in order to perform the reseedings. This way the implementation area of the BIST circuitry is further reduced. Experimental results demonstrate the advantages of the proposed LFSR reseeding approach over the already known reseeding techniques.