Low Transition-Generalized Linear Feedback Shift Register Based Test Pattern Generator Architecture for Built-in-Self-Test

Madjid Madjid

doi:10.3844/jcssp.2012.815.821

Abstract

Problem statement: In Built-In Self-Test (BIST), test patterns are ge nerated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by Linear Feedback Shift Registers. This nor mally requires more number of test patterns for testing the architectures which need long test time . Approach: This study presents a novel test pattern generation technique called Low-Transition Generali zed Linear Feedback Shift Register (LT-GLFSR) and it was also called Bipartite GLFSR. Intermediat e pattern (Bipartite technique) inserted in between consecutive test patterns generated by GLFSR was called LT-GLFSR technique which was enabled by a non overlapping clock scheme. Low-transition generalized linear feedback shift registers (LT-GLFSR), was used in a circuit under test to reduce the aver age and peak power during transitions. LT-GLFSR pattern generator would generate patterns with high er degree of randomness and high correlation between consecutive patterns would have efficient area impl ementation. LT-GLFSR did not depend on circuit under test and hence it could be used for both BIST and scan-based BIST architectures. Results/Conclusion: Simulation results show that this technique has re duction in power consumption and high fault coverage with minimum number of test patterns. The results also show that it reduces th e peak and average power consumption during test for ISCAS'89 bench mark circuits.

Highlights

Importance of testing in Integrated Circuit is to improve the quality in chip functionality that is applicable for both commercially and privately produced products
Built-In Self-Test (BIST) can provide high speed, in system testing of the CircuitUnder-Test (CUT) (Pradhan et al, 2005; Pradhan and Gupta, 1991). This is crucial to the quality component of testing. (Chatterjee et al, 2003) discussed that stored pattern BIST, requires high hardware overhead due to memory devices required to store pre computed test patterns, pseudorandom BIST, where test patterns are generated by pseudorandom pattern generators such as Linear Feedback Shift Registers (LFSRs) and Cellular Automata (CA), required very little hardware overhead
Achieving high fault coverage for CUTs that contain many Random Pattern Resistant Faults (RPRFs) only with random patterns generated by an LFSR or CA often requires unacceptably long test sequences thereby resulting in prohibitively long test time

Summary

INTRODUCTION

Importance of testing in Integrated Circuit is to improve the quality in chip functionality that is applicable for both commercially and privately produced products. Nourani et al (2008) deals with a low power test pattern generation for BIST applications It exploits Low Transition LFSR which is a combination of conventional LFSR and insertion of intermediate patterns (bipartite and random Insertion Technique) between sequences of patterns generated by LFSR that can be implemented by modified clock scheme as at-speed testing and reduced need of expensive Proposed work: This study presents a new test pattern external Automatic Test Equipment (ATE). Corno et al (2000) proposed a cellular automata algorithm for test pattern generation in combinational logic circuits This maximizes the possible fault coverage and minimizes length of the test vector sequences. A low power/energy BIST architecture based on modified clock scheme test pattern generator was discussed (Girard et al, 2001), it has been proposed inserts intermediate patterns between its original pairs. The favorable features of LT-GLFSR in terms of performance, fault coverage and power consumption are verified using the ISCAS benchmarks circuits

MATERIALS AND METHODS

RESULTS

DISCUSSION

CONCLUSION