Power Reduction in BIST Design Based on Genetic Algorithm and Vector-Inserted TPG

Abstract

A test pattern generator (TPG) for reducing power consumption during built-in self-test (BIST) application is proposed. It consists of an n-stage linear feedback shift register (LFSR) and some control logic, which makes the actual clock frequency of the LFSR become 1/m that of the original one, thereby, lowering the transition density at the LFSR. Thus, (m-1) vectors are inserted between successive test patterns generated by the original LFSR, during the cycles when the LFSR is unactuated. The number of inserted vectors and the location where some bits change between successive vectors are achieved by using optimization based on genetic algorithm (GA). Experimental results based on the ISCAS'85 benchmark circuits were reported to demonstrate the effectiveness of our approach on reducing the peak power consumption, and also on reducing the total power and the average power consumption, without losing stuck-at fault coverage.