Abstract
This paper proposes a low-cost test pattern generator for scan-based built-in self-test (BIST) schemes. Our method generates broadcast-based multiple single input change (BMSIC) vectors to fill more scan chains. The proposed algorithm, BMSIC-TPG, is based on our previous work multiple single-input change (MSIC)-TPG. The broadcast circuit expends MSIC vectors, so that the hardware overhead of the test pattern generation circuit is reduced. Simulation results with ISCAS’89 benchmarks and a comparison with the MSIC-TPG circuit show that the proposed BMSIC-TPG reduces the circuit hardware overhead about 50% with ensuring of low power consumption and high fault coverage.
Highlights
Nowadays VLSI testing is always used to ensure the correctness and reliability of the finished chip [1], but we encountered some problems during VLSI testing
Because the based multiple single input change (BMSIC)-TPG proposed in this paper was designed to overcome the drawback of the previous method [6], we compare the performance of BMSIC with our previous method [6]
This paper proposes a low-cost test pattern generation method BMSIC-TPG based on our previous work multiple single-input change (MSIC)-TPG, which can take into account both low power consumption and satisfactory fault coverage [6]
Summary
Nowadays VLSI testing is always used to ensure the correctness and reliability of the finished chip [1], but we encountered some problems during VLSI testing. This will lead to a large test power consumption during the test To solve this problem, a method of MSIC test pattern generation combining a pseudo-random sequence with a low-transition sequence has been proposed in paper [6]. A method of MSIC test pattern generation combining a pseudo-random sequence with a low-transition sequence has been proposed in paper [6] It can consider both high fault coverage and low power consumption [10,11]. A novel low-cost BIST architecture using test pattern broadcast circuits called broadcast-based multiple single input charge (BMSIC)-TPG has been developed. This method reduces the area overhead, and it scores well in power consumption and fault coverage.
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