A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST

Abstract

We present a new scan-based built-in self-test (BIST) technique, which is based on weighted scan-enable signals and a reconfigurable scan-forest architecture. A testability measure is proposed to guide test pattern generation and produce patterns with few care bits. This approach can effectively reduce the amount of test data that needs to be stored on-chip. The proposed BIST method relies on the pseudorandom and deterministic phases. The scan-forest architecture is configured as a single scan tree for deterministic test vector application in the second phase. It is found that a linear feedback shift register, with size equal to the maximum number of the care bits in the deterministic patterns for the random-resistant faults, is sufficient to encode deterministic vectors for the benchmark circuits. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method for single stuck-at faults. In addition, experimental results show that the patterns applied to the circuit under test provide more n-detection than those applied by a traditional scan-chain architecture with a single test session.