Low Transition Test Pattern Generator Architecture for Built-in-Self-Test

Mohamed Mohamed

doi:10.3844/ajassp.2012.1396.1406

Abstract

Problem statement: In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by linear feedback shift registers. This normally requires more number of test patterns for testing the architectures which need long test time. Approach: This study presents a novel test pattern generation technique called Low-Transition Generalized Linear Feedback Shift Register (LT-GLFSR) with bipartite (half fixed) and bit insertion (either 0 or 1) techniques. Intermediate patterns (by bipartite and bit (either 0 or 1) insertion technique) inserted in between consecutive test patterns generated by GLFSR which is enabled by a non overlapping clock scheme. This process is performed by finite state machine generate sequence of control signals. Low-Transition Generalized Linear Feedback Shift Registers (LT-GLFSR), are used in a circuit under test to reduce the average and peak power during transitions. LT-GLFSR patterns high degree of randomness and correlation between consecutive patterns. LT-GLFSR does not depend on circuit under test and hence it is used for both BIST and scan-based BIST architectures. Results and Conclusion: Simulation results prove that this technique has reduction in power consumption and high fault coverage with minimum number of test patterns. The results also show that it reduces the peak and average power consumption during test for ISCAS’89 bench mark circuits.

Highlights

Importance of testing in Integrated Circuit is to improve the quality in chip functionality that is applicable for both commercially and privately produced products
Chatterjee and Pradhan (2003) discussed that stored pattern Built-In Self-Test (BIST), requires high hardware overhead due to memory devices is in need to store pre computed test patterns, pseudorandom BIST, where test patterns are generated by pseudorandom pattern generators such as Linear Feedback Shift Registers (LFSRs) and Cellular Automata (CA), required very little hardware overhead
Achieving high fault coverage for CUTs that contain many Random Pattern Resistant Faults (RPRFs) only with random patterns generated by an LFSR or CA often requires unacceptably long test sequences thereby resulting in prohibitively long test time

Summary

INTRODUCTION

Importance of testing in Integrated Circuit is to improve the quality in chip functionality that is applicable for both commercially and privately produced products. Solutions that are commonly applied to pattern generation for BIST applications It exploits relieve the extravagant power problem during test Low Transition LFSR which is a combination of include reducing frequency and test scheduling to avoid hot spots. Prior work: Pradhan et al (1999) presented a consumption is more in test pattern generator and GLFSR, a combination of LFSR and cellular arrays, CUT. Algorithm for test pattern generation in combinational logic circuits This maximizes the possible fault Proposed work: This study presents a new test pattern coverage and minimizes length of the test vector generator for low-power BIST (LT-GLFSR), which can sequences. The favorable features of LT-GLFSR in terms of performance, fault coverage and power consumption are verified using the ISCAS benchmarks circuits

MATERIALS AND METHODS

RESULTS

DISCUSSION

CONCLUSION