A review on power optimization of linear feedback shift register (LFSR) for Low power built in self test (BIST)

Abstract

A new low transition test pattern generator using a linear feedback shift register (LFSR) called LT-LFSR reduce the average and peak power of a circuit during test by generating three intermediate patterns between the random patterns. The goal of having intermediate patterns is to reduce the transitional activities of Primary Inputs (PI) which eventually reduces the switching activities inside the Circuit under Test (CUT) and hence, power consumption. The random nature of the test patterns is kept intact. The area overhead of the additional components to the LFSR is negligible compared to the large circuit sizes. The experimental results for ISCAS'85 and '89 benchmarks, confirm up to 77% and 49% reduction in average and peak power, respectively.