Sampling Clock Research Articles

A sampled-data feedforward programmable time-mode comb filter

In this work, a sampled-data feedforward comb filter suitable for time-mode signal processing (TMSP) is proposed. In the proposed system the input voltage is sampled and converted to a pulse-width (PWM); the pulse width is proportional to the input amplitude. The pulse width is the quantity which is being processed by the time-mode feedforward comb filter. Both input and output are synchronous with the sampling clock. The benefits of the proposed filter topology are (a) the modular and (b) hierarchical design which can be dealt with as a pure digital comb filter implementation counterpart. The frequency response of the proposed filter is digitally programmable. As a result, this filter can be used as building block for the implementation of higher-order time-mode systems. The comb filter was designed and verified through post-layout simulations in TSMC 65 nm technology process. The sampling rate was 5 MHz, the voltage supply was 1.2 V, consuming 540 μW for the use of 9-unit delay tap network and occupying a total area of 254 μm × 160 μm.

Research on Clock Synchronization of Data Acquisition Based on NoC

Data acquisition based on network-on-chip (NoC) technology is a high-sampling-rate data acquisition scheme using low-sampling-rate analog–digital conversion (ADC) chips. It has the characteristics of multi-task parallel communication, being global asynchronous, local synchronous clock distribution, high throughput, low transmission latency, and strong scalability. High-speed data acquisition is realized through the combination of an on-chip network and time-interleaved data acquisition technology. In the time-interleaved sampling technique, the precision of clock synchronization directly affects the precision of sampling. Based on the proposed NOC data acquisition scheme, an improved White Rabbit clock synchronization protocol is applied to high-speed data acquisition to achieve high-precision synchronization of multi-channel time-interleaved sampling clocks. Firstly, the offset of the master clock and slave clock is determined by the PTP protocol, and the offset is corrected to achieve rough synchronization between the master clock and slave clock. Secondly, a digital dual-mixer time difference (DDMTD) is used to measure the phases of the master and slave clocks. After that, the phase of the slave clock is corrected through the dynamic phase-shift function of the clock’s phase-locked loop (PLL). Finally, according to the simulation results in Modelsim, the average absolute error of a TI-ADC sampling clock can be less than 20 ps.

Direct Digital RF Transceiver Technology for Millimeter‐Wave DBF Systems

AbstractDigital RF technology has been developed and has been applied to below 6 GHz wireless applications. By replacing the IC die consumptive RF/analog circuit blocks by digital signal processor and circuit, digital rich/small transceivers can be realized. Since the foundation of this technology is based on the Nyquist theory, the operational frequency of the circuit has been limited by the Nyquist frequency (=1/2 of sampling clock frequency). As a result, the maximum operational RF frequency of existing digital RF technology was below 6 GHz. In this paper, a new direct digital RF technology that utilizes the higher‐order Nyquist zones is introduced. This technology enables handling RF signal in beyond Nyquist frequency range which means over 6 GHz range. The results of fabricated 26/28 GHz‐band transmitter/receiver are reviewed. Since the transceiver architecture with the proposed technologies does not require an RF local oscillator and up/down converters, it is suitable for microwave/millimeter‐wave multi‐antenna systems such as next generation satellite on‐board digital beam forming and Beyond 5G fully digital Massive multiple‐input multiple‐output systems.

Multi-bit per cycle true random number generator based on XOR-XNOR ring oscillator unit

To achieve a fast and resource-efficient entropy source, we present a novel oscillator unit, called XOR-XNOR ring oscillator (XXRO) which consists of an XOR gate and an XNOR gate. The XXRO unit has an internal feedback loop that allows the accumulation of jitter within the unit. Connecting multiple XXRO units forms a new entropy source. We utilize the differences between the XXRO units in the entropy sources to output two bits pre cycle, increasing the throughput of the True Random Number Generator (TRNG) while optimizing the use of hardware resources. In this paper, we use four proposed entropy source to form a TRNG, by sampling the two outputs of each entropy source individually and performing an XOR computation based on the corresponding positions to obtain random numbers. Experimental results indicate that when working at a throughput of 250 Mbps under a 125 MHz sampling clock, both outputs of the proposed TRNG pass the randomness tests and other performance tests.

A 1-16-Gb/s All-Digital Clock and Data Recovery With a Wideband, High-Linearity Phase Interpolator

An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature sampling clocks from 4 to 8 GHz. A new low-power two-step PI (TSPI) with high linearity over 4–8 GHz range is presented. The all-digital CDR control loop adopts a multimode phase detection scheme enabling continuous data rate support. The digital architecture not only eliminates the large filtering capacitor but also makes the design more tolerant to process, voltage, and temperature variations. The CDR core occupies 0.088 mm2 in a commercial 65-nm CMOS technology and consumes 73.1 mA at 16 Gb/s from a 1.2 V power supply. The differential nonlinearity of the PI is measured to be within 0.48 LSB. The measurement results show that this CDR can function at the proposed phase detection modes and is able to exceed the synchronous optical networking (SONET) OC-192 jitter tolerance mask at least by 0.2 unit interval at high frequencies (4–100 MHz) with a $2^{31}-1$ pseudorandom binary sequence data pattern at 10 Gb/s and a target bit error rate of $10^{-12}$ .

A 12-bit, 27.8-ps resolution, Anti-PVT variation multi-parallel sampling based coarse-fine TDC for LiDAR sensors

This paper presents a multi-parallel sampling based coarse-fine time-to-digital converter (TDC) with sub-gate delay resolution, large measurement range and high conversion rate for light detection and ranging (LiDAR) sensors. The fine-TDC is designed based on a voltage-controlled delay line (VCDL) but with multi-parallel sampling D flip-flop (DFF) groups to achieve a sub-gate delay resolution based on multi-phase interpolation. These DFF groups are triggered by several successively delayed sampling clocks that generated by a phase-locked loop (PLL) based multi-phase clock generator. The coarse-TDC composed of a coarse counter and a logical control circuit (LCC) is designed to enlarge the measurement range. The LCC is used to calibrate and guarantee the coarse counter neither over-counted nor under-counted. Since the delay of delay units in fine-TDC is also voltage-controlled by another PLL, the resolution of this proposed TDC is robust to process-voltage-temperature (PVT) variation. Besides, this proposed TDC architecture also has the property of dynamic element matching (DEM), which contributes to mitigate the impact of device mismatch and scramble the quantization noise. The post-layout simulations demonstrate a 12-bit, 27.8-ps time resolution, 0.86-LSB DNL, 0.92-LSB INL with 13.6-mW power consumption at 33.3-MS/s under a 1.8-V supply.

An improved wide-range, low-complexity, fully-parallel digital background timing mismatch calibration method for dual-channel TIADC based on perfect reconstruction filter bank

This paper presents a fully-digital background calibration method for calibrating timing mismatch in dual-channel time-interleaved analog-to-digital converter (TIADC). The proposed method estimates timing mismatch by performing correlation calculations on the outputs of sub-channels and corrects this mismatch using the improved perfect reconstruction filter bank (PRFB). The PRFB, which is improved by employing a polynomial fitting method, offers superior performance with fewer filter taps and extends the timing mismatch correction capability to almost the entire sampling clock cycle. The improved PRFB uses only one twentieth of the taps used in the original PRFB, and its dual-channel FIR filters have anti-symmetric taps. To enhance the real-time calibration capability of the system, this paper gives a fully-parallel hardware structure for calibrating offset, gain, bandwidth, and timing mismatches. The effectiveness of the proposed hardware structure is verified through a 10-bit 3GS/s dual-channel TIADC test platform. Simulation and measurement results show that the proposed calibration method significantly improves the signal-to-noise-and-distortion (SNDR) and spurious-free dynamic range (SFDR) of both single-tone and multi-tone input signals, which makes the proposed method a viable solution for practical TIADC applications.

Information Recovery for Signals Intercepted by Dual-Channel Nyquist Folding Receiver with Adjustable Local Oscillator

Conventional Nyquist folding receiver (NYFR) uses zero crossing rising (ZCR) voltage times to control the RF sample clock, which is easily affected by noise. Moreover, the analog and digital parts are not synchronized so that the initial phase of the input signal is lost. Furthermore, it is assumed in most literature that the input signal is in a single Nyquist zone (NZ), which is inconsistent with the actual situation. In this paper, we propose an improved architecture denominated as a dual-channel NYFR with adjustable local oscillator (LOS) and an information recovery algorithm. The simulation results demonstrate the validity and viability of the proposed architecture and the corresponding algorithm.

A fully integrated fast transient response digital low-dropout regulator with built-in sampling clock

A fast transient digital low-dropout regulator (LDO), in which the sampling clock is adaptively generated by a voltage-controlled oscillator, is proposed in this paper. In steady state, the LDO operates at a fine-regulation mode and the oscillator generates a low-frequency clock for low power consumption. When the output voltage exceeds the boundaries of overshoot or undershoot, the LDO switches into a coarse-regulation mode with a higher clock frequency and a shorter response time. To enhance the transient performance at near-threshold region, a three-stage high-speed comparator is further introduced. The designed digital LDO was fabricated in standard 180 nm CMOS process. Measured results show that the maximum variation of transient output voltage is 120 mV while the load steps from 2 to 22 m A with a 10 ns edge time. The proposed LDO obtains a low quiescent current of 14.5 μA with a 0.0587 ps figure of merit.

A 17.6-Bit 800-SPS Energy-Efficient Read-Out IC With Input Impedance Boosting

A 17.6-bit, 800-sample-per-second (SPS) read-out integrated circuit has been implemented for a bridge sensor. The read-out integrated circuit has a capacitively-coupled instrumentation amplifier (CCIA) with a sensor offset voltage compensation circuit, an amplifier offset voltage compensation circuit, and an input impedance boosting loop (IBL). Followed by the CCIA, a programmable-gain third-order discrete-time incremental delta-sigma (ΔΣ) analog-to-digital converter (ADC) with an output data-rate of 12.8 kHz shortens the sensing time to reduce the static power consumption of the resistive bridge sensor and the read-out IC. To boost the input impedance of the CCIA, the system-level input and output choppers operate at a frequency of 12.8 kHz. The ΔΣ modulator converts the modulated signal to digital with a sampling clock of 4 MHz. The system-level chopping reduces the residual offset and the low-frequency noise with an on-chip cascade of integrators (CoI) filter. Implemented in a 0.13 μm CMOS process, the read-out circuit achieves an input impedance of 22 MΩ at a data-rate of 800 SPS, a sensor offset compensation range of ± 350 mV, a maximum effective resolution of 17.6 bits, and an input-referred noise of 1.72 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</sub> at a gain of 128. It draws an average current of 106.3 μA from a 3 V supply and 1.3 μA from a 1.5 V supply.

A 77.3-dB SNDR 62.5-kHz Bandwidth Continuous-Time Noise-Shaping SAR ADC With Duty-Cycled Gm-C Integrator

This article presents a first-order continuous-time (CT) noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC). Different from other NS-SAR ADCs in literature, which are discrete-time (DT), this ADC utilizes a CT Gm-C integrator to realize an inherent anti-aliasing function. To cope with the timing conflict between the DT SAR ADC and the CT integrator, the sampling switch of the SAR ADC is removed, and the integrator is duty cycled to leave 5% of the sampling clock period for the SAR conversion. Redundancy is added to track the varying ADC input due to the absence of the sampling switch. A theoretical analysis shows that the 5% duty-cycling has negligible effects on the signal transfer function (STF) and the noise transfer function. The output swing and linearity requirements for the integrator are also relaxed thanks to the inherent feedforward path in the NS-SAR ADC architecture. Fabricated in 65-nm CMOS, the prototype achieves 77.3-dB peak signal-to-noise and distortion ratio (SNDR) in a 62.5-kHz bandwidth while consuming <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$13.5~\mu \text{W}$ </tex-math></inline-formula> , leading to a Schreier figure of merit (FoM) of 174.0 dB. Moreover, it provides 15-dB attenuation in the alias band.

A Photonic Time-Interleaved ADC Architecture Based on Optical Clock Distribution and Elector-Optical Modulation Technology

A photonic time-interleaved analog-to-digital conversion (PTIADC) scheme by exploring optical clock distribution technology and elector-optical modulation technology is presented in this work. In the proposed PTIADC system, the interleaved sampling clocks for several channel analog-to-digital converters (ADCs) are implemented by optical clocks. A proof-of-concept experiment with a four-channel 400 MS/s PTIADC system has been achieved, and the performance has been experimentally demonstrated. Experimental results show that the proposed method can offer four-channel clock signals with low-timing jitters. The effective number of bits (ENOB) of the constructed PTIADC is ∼6 bits. Additionally, timing mismatch calibration via conveniently adjusting the length of optical delay lines produces a 26 dB spur suppression.

Design of Low Probability Detection Signal with Application to Physical Layer Security

In this work, we mainly focus on low probability detection (LPD) and low probability interception (LPI) wireless communication in cyber-physical systems. An LPD signal waveform based on multi-carrier modulation and an under-sampling method for signal detection is introduced. The application of the proposed LPD signal for physical layer security is discussed in a typical wireless-tap channel model, which consists of a transmitter (Alice), an intended receiver (Bob), and an eavesdropper (Eve). Since the under-sampling method at Bob’s end depends very sensitively on accurate sampling clock and channel state information (CSI), which can hardly be obtained by Eve, the security transmission is initialized as Bob transmits a pilot for Alice to perform channel sounding and clock synchronization by invoking the channel reciprocal principle. Then, Alice sends a multi-carrier information-bearing signal constructed according to Bob’s actual sampling clock and the CSI between the two. Consequently, Bob can coherently combine the sub-band signals after sampling, while Eve can only obtain a destructive combination. Finally, we derived the closed-form expressions of detection probability at Bob’s and Eve’s ends when the energy detector is employed. Simulation results show that the bit error rate (BER) at Alice’s end is gradually decreased with the increase in the signal-to-noise ratio (SNR) in both the AWGN and fading channels. Meanwhile, the BER at Eve’s end is always unacceptably high no matter how the SNR changes.

A 128-channel time-to-digital converter based on the 24-phase shift-clock sampling method for RPC

The Resistive Plate Chamber (RPC) are widely used in high energy physics (HEP) experiments. In recent years, new designs and application scenarios of RPCs abound, and an advanced time-to-digital converter (TDC) system is in demand. The TDC implemented in the field-programmable gate array (FPGA) is widely used in HEP experiments with changeable conditions as a flexible time measurement method. This article presents a multi-phase shift-clock sampling FPGA-based TDC with 128 channels. The TDC module is implemented in a Xilinx Kintex-7 FPGA. The sampling clock period (2.22 ns) is subdivided into 24 phases to achieve finer time resolution. The TDC performance measurements show that the root-mean-square (RMS) time resolution of the TDC module in the time interval measurement is 45.3 ∼ 57.7 ps, and the integral nonlinearity (INL) is smaller than 0.2368 least significant bit (LSB). In addition, some target designs are made to adapt to the application scenarios. This article also shows measurement results acquired from an RPC by this TDC. This TDC was used to measure the RPC efficiency plateau and the TOT of the RPC readout signal.

Time-Stable Receiving System With Local Digitization Based on a Dithered Sample Clock

We present a time-stable receiving system for broadband signals transmitted via a 25 km fiber optic link. The timing jitter of the signal induced by the transmission link is precisely eliminated after the signal is digitized with a dithered sample clock. The dithered clock is generated from the phase of a voltage-controlled oscillator, introducing the same transmission timing jitter of the link. Therefore, it can withstand an unlimited range of transmission delay variations without using any optical or electrical delay lines. Experimentally, binary phase-shift keying signals with bandwidths of several hundred MHz and different carrier frequencies are transmitted and received by the proposed system. The root mean square of the calculated timing jitters of the received signals is decreased to the order of picosecond. The simple remote end and immunity to environmental perturbations of the proposed scheme make it an ideal candidate for a large-scale distributed antenna system.

A dynamically reconfigurable entropy source circuit for high-throughput true random number generator

—True random number generator is an important hardware security primitive. Entropy source is the key to the design of a high-throughput true random number generator. To improve the throughput of a true random number generator while maintaining low hardware overhead, a novel entropy source circuit using ring oscillator with dynamically reconfigurable delay chain is proposed in this paper. The proposed entropy source exploits both signal jitter and circuit metastability. It consists of a seventh-order cycle shift register, seven 2-1MUXs and a core loop delay chain that is composed of inverters in series. Under the control of a high-frequency clock, the cycle shift register generates state transitions to control the output of MUXs, which in turn changes the number of inverters connected in the delay chain, switching the operation of the ring between steady and oscillating states. The outputs of five entropy sources are sampled and further XOR-ed with D flip-flops at a sampling clock of 400 MHz to obtain true random numbers. The proposed TRNG is implemented on the Xilinx Virtex-6 FPGA. The random numbers are captured in real-time using the Xilinx ChipScope and the TRNG is tested using the standard test specifications. The experimental results show that when working under a throughput of 400 Mbps, the proposed TRNG passes the NIST SP800-22 and the NIST SP800–90 B tests with a passing rate greater than 98% and a minimum entropy index per bit greater than 0.99. It also passes the relevant performance tests including autocorrelation test, restart test, deviation test, and temperature and voltage fluctuation test, and it has low hardware overhead.

A 121 dB SNDR Zoom ADC Using Dynamic Amplifier and Asynchronous SAR Quantizer

This paper presents a discrete-time zoom analog-to-digital converter (ADC) for low-bandwidth high-precision applications. It uses a coarse-conversion 5-bit asynchronous self-timed SAR ADC combined with a fine-conversion second-order delta-sigma modulator to efficiently obtain a high signal-to-noise distortion ratio (SNDR). An integrator circuit using a high-gain dynamic amplifier is proposed to achieve higher SNDR. The dynamic amplifier uses a switched tail current source to operate periodically, simplifying the common-mode feedback circuit, reducing unnecessary static current, and improving the PVT robustness. Dynamic error correction techniques, such as redundancy, chopping, and dynamic element matching (DEM) are used to achieve low offset and high linearity. And a 2-bit asynchronous SAR quantizer with an embedded feed-forward adder is used in the second-order delta-sigma modulator to reduce the quantization noise caused by redundancy, and further achieve higher energy efficiency. Simulation results show that the ADC achieves a peak SNDR of 121.1 dB in a 390 Hz bandwidth at a 200 kHz sampling clock while consuming only 170 μW from a 2.5 V supply and the core area is 0.55 mm2. This results in a Schreier figure of merit (FoM) of 184.7 dB.

Unsteady Aerodynamic Lift Force on a Pitching Wing: Experimental Measurement and Data Processing

This work discusses the experimental challenges and processing of unsteady experiments for a pitching wing in the low-speed wind tunnel of the Vrije Universiteit Brussel. The setup used for unsteady experiments consisted of two independent devices: (a) a position control device to steer the pitch angle of the wing, and (b) a pressure measurement device to measure the aerodynamic loads. The position control setup can pitch the wing for a range of frequencies, amplitude, and offset levels. In this work, a NACA-0018 wing profile was used with an aspect ratio of 1.8. The position control and the pressure measurement setups operate independently of each other, necessitating advanced signal processing techniques to synchronize the pitch angle and the lift force. Furthermore, there is a (not well-documented) issue with the (sampling) clock frequency of the pressure measurement setup, which was resolved using a fully automated spectral analysis technique. The wing was pitched using a simple harmonic sine excitation signal at eight different offset levels (between 6° and 21°) for a fixed amplitude variation (std) of 6°. At each offset level, the wing was pitched at five different frequencies between 0.1 Hz and 2 Hz (that correspond to reduced frequencies k ranging from 0.006 to 0.125). All the experiments were conducted at a fixed chord-based Reynolds number of 2.85 × 105. The choice of operating parameters invokes the linear and nonlinear behavior of the wing. The linear unsteady measurements agreed with the analytical results. The unsteady pressure measurements at higher offset levels revealed the nonlinear aerodynamic phenomenon of dynamic stall. This confirms that a nonlinear and dynamic model is required to capture the salient characteristics of the lift force on a pitching wing.

Distributed receiving system with local digitization and combination for SNR enhancement.

We demonstrate an X-band distributed receiving system with 4 remote ends for signal-to-noise ratio (SNR) enhancement. The X-band analog signal received by 4 remote ends is first transmitted to the local end through optical fiber links and is then down-converted with a photonic method for digitization and further coherent combination. Finally, a combined signal with a higher SNR can be obtained. In the proposed system, a frequency-tunable single-tone signal is stably transmitted to the remote end for both down-converting the received signal and for generating a dithered sample clock to eliminate the transmission delay jitter with an unlimited compensation range. Experimentally, X-band binary phase shift keying signals are used for system performance evaluation. After 20 to 25 km transmission, the relative timing drifts between different links are at the order of picoseconds, and a near-theoretical SNR enhancement is achieved. The proposed scheme has a simple remote structure with no need for time synchronization, increasing its signal combining precision, flexibility, and scalability, making it an ideal candidate for long-distance weak signal detection.

Square wave reference digital lock-in detection using non-orthogonal demodulation

Digital lock-in detection technique is commonly used to measure the amplitude and phase of a selected frequency signal. The technique which uses a square wave as the reference signal has an advantage of easier implementation and higher computational efficiency compared to that uses a sine wave. However, one constraint for a square wave reference digital lock-in is that the sampling rate must be the integral multiple of 4 of all the signal frequencies. As the sampling clock may not always be able to set to the integral multiple of 4 of the signal frequencies, the constraint brings inconvenient for the implementation. Presented in this paper is a novel algorithm for square wave digital lock-in detection in which the sampling frequency doesn't have to meet the constraint. The algorithm allows frequency sweep measurements with a fixed sampling rate. For different relationships between the sampling rate and the signal frequency, different calculation equations are provided in this paper. Simulations and actual experiments show the feasibility of the proposed algorithm.