Sampling Clock Research Articles

A Baseband Wireless VNA for the Characterization of Multiport Distributed Systems

Frequency characterization of spatially large structures has become increasingly required, mostly in the fields of structural health monitoring (SHM) and communication systems based on nonconventional media. When the ports of the system under measurement are far apart, methods based on traditional wired instruments become unattractive for field applications, due to the increased complexity, cost, and signal integrity-related issues. Aiming toward removing the wired connection from the ports of the system under test and the elaboration unit (EU), the main issue to be dealt with is the time synchronization of measurements at the ports. This contribution proposes a solution to such an issue by presenting a Wireless Vector Network Analyzer (WVNA), suitable for the characterization of distributed systems. For this purpose, a wireless synchronization scheme is proposed, which is based on the disciplining of the signal sampling clock from the 1-pulse/s reference signal. The proposed synchronization method reduces clock jitter at different ports at 1.13 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> over a 300-s observation interval. The hardware and software implementation of the system are detailed and experimental results proving its operation are provided.

High-resolution time-to-digital converters (TDCs) with a bidirectional encoder

A high-resolution time-to-digital converter (TDC) based on wave union (four-edge WU A), dual-sampling, and sub-TDL methods is proposed and implemented in a 16-nm Xilinx UltraScale + field-programmable gate array (FPGA). We combine WU and dual-sampling techniques to achieve a high resolution. Besides, we use the sub-TDL method and the proposed bidirectional encoder to suppress bubbles and encode four-transition pseudo thermometer codes efficiently. Experimental results indicate the proposed TDC achieves a 0.4 ps resolution with a 450 MHz sampling clock and a less than 9 ps RMS precision from 0 ns to 100 ns (achieving a 3.06 ps RMS precision in the best-case scenario). These characteristics make this design suitable for particle physics, biomedical imaging (such as positron emission tomography, PET), and general-purpose scientific instruments.

Robust Synchronized Data Acquisition for Biometric Authentication

Owing to its unique, concealment and easy customization by combining different wrist and hand gestures, high-density surface electromyogram (HD-sEMG) is recognized as a potential solution to the next generation biometric authentication, which usually adopts a wireless body sensor network (BSN) to acquire the multi-channel HD-sEMG biosignals from distributed electrode arrays. For more accurate and reliable classification, biometric authentication requires the distributed biosignals to be sampled simultaneously and be well aligned, which means that the sampling jitters among the arrays need to be tiny. To synchronize data sampling clocks of a cluster of BSN nodes for biometric authentication, this article modifies the packet-coupled oscillators protocol by using a dynamic controller (D-PkCOs). This protocol only involves one-way single packet exchange, which reduces the communication overhead significantly. For the purpose of maintaining precise sampling of these BSN nodes subject to drifting clock frequency and varying delays, the dynamic controller is designed via the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$H_\infty$</tex-math></inline-formula> robust method, and it is proved that all the BSN nodes’ sampling jitters are bounded. The experimental results demonstrate that the D-PkCOs protocol can keep the sampling jitters less than a microsecond in a 10-node IEEE 802.15.4 network. The application of D-PkCOs to the BSN shows that the HD-sEMG signal with a high signal-to-noise ratio is obtained, which leads to better gesture classification performance.

A Single-Bit Incremental Second-Order Delta-Sigma Modulator with Coarse-Fine Input Buffer

This paper presents an incremental second-order delta-sigma modulator with a coarse-fine input buffer in 180-nm CMOS. The modulator’s architecture was implemented as a second-order cascade of integrators with a feedback structure. The switched-capacitor integrator was operated in discrete time, with high-gain amplifiers required to achieve improved performance during the integration phase. The amplifier comprised rail-to-rail input and gain-boosted cascode intermediate stages, thus achieving a high gain and wide input voltage range. The circuit adopts a coarse-fine buffer for higher performance. The coarse buffer is operated first to enable fast settling through a high slew rate, followed by the fine buffer to satisfy the low-noise and high-accuracy characteristics. The fine buffer has a smaller current consumption with higher power efficiency. The experiment results show that the proposed input buffer achieved a 13.14 effective number of bits and an 80.87 dB signal-to-noise and distortion ratio. The modulator operates a single bit and sampling clock at 125 kHz. The proposed delta-sigma modulator was operated at 1.8 V. The proposed circuit was designed using a standard 0.18-μm CMOS process with an active area of 1.06 mm2. The total current consumption with the coarse-fine buffer was 1.374 mA.

Research on a step delay method in sequential equivalent time sampling (ETS)

Sequential equivalent time sampling (ETS) has been extensively used in data acquisition instruments (e.g., sampling oscilloscopes and time domain reflectometers). A novel step delay method is proposed based on the frequency difference to obtain a higher sampling rate in sequential ETS. It is different from the classic step delay methods and is capable of increasing the sampling rate. The sampling clock and the repetitive signal are taken as examples in this study. The time-frequency conversion relationship indicates that a fine step delay will be generated in the time domain if there is a frequency difference between the two in the frequency domain. The core of the proposed method is the selection of the appropriate frequency difference (step delay) according to the desired equivalent sampling rate. Two experiments were performed to verify the proposed method. The feasibility of the proposed method is verified using a digital storage oscilloscope. Four cases are examined in the experiment, and the final equivalent sampling rate is obtained as 5 PS/s for the equivalent sampling of a 4.999 995GHz (or higher) signal. A data acquisition system with a 10 MS/s real-time sampling rate is designed to verify the feasibility of the proposed method, obtaining a theoretical equivalent sampling rate of 585 GS/s. The theoretical equivalent sampling rate and the examined equivalent sampling rate are consistent. The equivalent sampling waveform and real-time sampling waveform of a 1GHz signal are compared, and the comparison result suggests that the proposed method can acquire more waveform information. The proposed method obtains a high equivalent sampling rate for repetitive signals, and techniques (e.g., oversampling) are given to obtain higher vertical resolution. The proposed method, combined with a sample-and-hold amplifier, can also achieve a higher analog bandwidth.

A 2.5 GS/s 7-Bit 5-Way Time-Interleaved SAR ADC With On-Chip Background Offset and Timing-Skew Calibration

This brief presents the on-chip background offset and timing-skew calibration of the 1-then-2b/cycle time-interleaved successive-approximation-register analog-to-digital converter (TI SAR ADC). For timing-skew between sub-ADC’s sampling clocks, a comparator offset-based window detector (WD) is used to adjust the clock edge misalignment. In addition, comparator offset calibration is considered both in terms of 1) global offset (between the offset-free reference comparator and the local reference comparator in each sub-ADC) and 2) local offset (between the local reference comparator and the rest of the comparators in the same sub-ADC). The proposed calibration sufficiently suppresses noise floor and spurs, and all calibrations are performed in the background without interfering with normal ADC operation. The prototype 5-way TI SAR ADC is fabricated in a 28 nm CMOS process and occupies a 0.03 mm2 area including on-chip calibration. With the proposed calibration, the prototype achieves SNDR of 40 dB at Nyquist input and consumes 7.57 mW, leading to the Walden figure of merit ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\text {FoM}_{W}}$ </tex-math></inline-formula> ) of 37.2 fJ/conversion-step.

Hybrid Cramer-Rao Bound on Carrier and Sampling Frequency Offset Estimation for OFDM Systems in Rayleigh Fading Channels

For the carrier frequency offset (CFO) and sampling (clock) frequency offset (SFO) estimation, the hybrid Cramer-Rao bound (HCRB) is developed when the CFO, SFO, information-bearing symbols are deterministic and channel coefficients are random. Both noise and channel coefficients are complex Gaussian. The HCRB is a lower bound on the mean squared estimation error for any unbiased estimator of a parameter. For the HCRB to be applicable, it is necessary for deterministic parameters to be identifiable (uniquely determined). Some necessary identifiability conditions of some deterministic parameters are found and presented. The HCRB is dependent on the initial time instant. The HCRB is used to assess the performances of some existing methods via simulation. Our results demonstrate that even the best performance is still around 10 dB higher than the HCRB. Further effort is needed to develop more accurate methods.

UTC Synchronized Signal Generation for Synchrophasors and Sampled Values Measurements

This article describes two methods and circuits for generation of a signal synchronized to the Coordinated Universal Time (UTC) time scale. The signal is used as a sampling clock for a synchrophasor and Sampled Values generation. Both methods use a PPS (Pulse Per Second) pulse as a synchronization signal. In the first method, the synchronization procedure is implemented entirely in a Field Programmable Gate Array (FPGA) device. The second method uses a microcontroller and a Temperature Compensated Voltage Controlled Crystal Oscillator (TCVCXO). The common feature of the presented methods is that they are cost effective and use a minimal number of components. This paper presents the implementation details of both methods as well as the measurement results, which show that the accuracy of the synchronized signals in both procedures makes them suitable for use in synchrophasors and sampled values measurements.

Improvement of a Sample Clock Offset Estimation Method Used in Passive Radar

Sample clock offset must be estimated in order to correctly demodulate an OFDM signal. Estimates are also required in passive radar processing, to produce a reference signal, which is properly matched to the transmission. A recently proposed clock offset estimation method for passive radar is found to be overly sensitive to measurement noise. However, the radar ambiguity surface is found to be unaffected by the specific errors engendered by this noise. The reasons for this are explored. An updated method based on state-space modeling and Kalman smoothing is proposed. This is found to restore clock offset estimation performance in cases of higher noise, achieving this with low processing latency. These improvements enable the method to be employed for other applications requiring high quality, time-critical clock offset estimation.

Metallic Ratio Equivalent-Time Sampling and Application to TDC Linearity Calibration

In LSI testing, equivalent time sampling techniques are frequently used because the input signals to the device under test and the sampling clock are controllable; when repetitive input signals are applied to the analog device under test, its output signals can be also repetitive. In this paper, we investigate an efficient waveform acquisition method with equivalent-sampling using the metallic ratio of the sampling frequency and the input frequency, which is expected to be used for on-line, short-time and simple analog/RF/mixed-signal IC testing. We reveal that metallic sampling technique can be a powerful tool for the TDC linearity calibration with the histogram method.

Robust Sampling Clock Recovery Algorithm for Wideband Networking Waveform of SDR

A novel technique for sampling clock recovery in a wideband networking waveform of a software defined radio is proposed. Sampling clock recovery is very important in wideband networking radio operation as it directly affects the Medium Access adaptive time slot switching rate. The proposed Sampling clock recovery algorithm consists of three stages. In the first stage, Sampling Clock Offset (SCO) is estimated at chip level. In the second stage, the SCO estimates are post-filtered to improve the tracking performance. We present a new post-filtering method namely Steady-State State-Space Recursive Least Squares with Adaptive Memory (S4RLSWAM). For the third stage of SCO compensation, a feedforward Lagrange interpolation based algorithm is proposed. Real-time hardware results have been presented to demonstrate the effectiveness of the proposed algorithms and architecture for systems requiring high data throughput. It is shown that both the proposed algorithms achieve better performance as compared to existing algorithms.

Resolution-Selective and Resolution-Adaptive 2 to 8-Bit Flash ADC for High-Speed Application-Independent IC (HS-AIIC)

Application-Specific ICs (ASIC) are manufactured in bulk for a long time. In this paper, an approach to High-Speed Application-Independent IC (HS-AIIC) design is discussed. A resolution-selective (RS) and resolution-adaptive (RA) 8-bit Flash ADC are designed for use in various high-speed applications. With the choice of resolution, one can work with the trade-off between speed, power consumption, and resolution for a particular application. The proposed resolution selection algorithm can be implemented for any set of resolutions for a flash ADC design. Further, an adaptive block is added to make the ADC design adaptive in nature so that we do not have to select a particular resolution manually. The proposed design entrusts on saving manufacturing cost and increases the functionality of ADC on a single chip. Proposed resolution adaptive 8-bit flash ADC design dissipates 512[Formula: see text]mW of power with an ENOB of 7.56 bits and SNDR of 46.27[Formula: see text]dB for 1[Formula: see text]GHz sampling clock pulse.

Clock Synchronized Transmission of 51.2 GBd Optical Packets for Optically Switched Data Center Interconnects

Optical switching has attracted significant attention in recent research on data center networks (DCNs) as it is a promising viable route for the further scaling of hyper scale data centers, so that DCNs can keep pace with the rapid growth of machine-to-machine traffic. It has been shown that optical clock synchronization enables sub-nanosecond clock and data recovery time and is crucial to high performance optically switched DCN. Moreover, the interconnect data rate is expected to increase from the current 100 Gb/s per fiber to scale to 800 Gb/s and beyond, requiring high baud rate signaling at >50 GBd. Thus, future optically switched DCN should support >50 GBd data transmission with optical clock synchronization. Here, we demonstrate the clock-synchronized transmission of 128-byte optical packets at 51.2 GBd and study the impact of reference clock phase noise on system performance, focusing on the tolerance to the clock phase misalignment that affects the system scalability and reliability. By comparing the tolerable sampling clock phase offsets using different reference clocks, we show that a clock phase offset window of about 8 ps could be achieved with a <0.2ps source clock. Furthermore, we model and numerically study the de-correlation of clock phase noise. This allows the total jitter to be estimated, and thereby, the estimation of the transmission performance for future generations of high baud rate, clock synchronized DC interconnects.

A Memory-Based Direct-Digital Frequency Synthesizer for Fractional Synchronization

This paper presents a fully integrated energy-efficient memory-based direct digital frequency synthesizer (DDFS). To overcome the limitation of using an accumulator and a Read-Only Memory (ROM) Lookup Table (LUT) within a DDFS, the proposed design utilizes a 6-bit memory with a configured mode of operation to synchronize the digital output clock with the input sampling clock. The proposed DDFS is able to tune the output phase and frequency once a phase rotator is used in the input clock path. To realize the proposed DDFS, a 6-bit memory in front-end and some analog blocks in back-end are employed. The prototype DDFS achieves jitter below 12.7 psrms integrated over a 100 MHz bandwidth with 28.25 Hz resolution while consuming less than 3 mW at sampling clock 3.12 GHz. The proposed DDFS is fabricated in a 0.9 V TSMC 7 nm CMOS process and occupies a core area of only 0.014 mm.

A 2.4–8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input–Output Phase Detection

This paper presents a phase rotator (PR)-based delay-locked loop (DLL) for a dynamic random-access memory interface in 28-nm CMOS technology. A direct input-output comparison using a sub-sampling technique reduces the effect of a timing mismatch of a replica delay line for synchronizing an input clock and output strobe clock. A divided clock samples the input clock for phase alignment. A 4-b analog-to-digital converter was used for input phase acquisition. The output phase is aligned with respect to the sampling clock phase using a bang-bang phase detector. Two DLLs for the input-output synchronization are implemented in a cascade structure, and the loop delay of the replica delay line is considerably reduced. In the proposed DLL, a PR delay line using an 8-phase clock generator is adopted for linearity to reduce the phase difference of the phase interpolation from π/2 to π/4. The resolution of the PR-DLL is 7-b of 2π, which consists of a 3-b coarse and a 4-b fine control. The DLL operates from 2.4 to 8 GHz, and the power dissipation at the maximum input frequency is 20.2 mW. The measured clock root mean square jitter was 1.68 ps. According to the simulation results, the phase mismatch between the input and output clocks was reduced by 80.5%.

A Low-Jitter and Low-Spur Charge-Sampling PLL

This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses the reference spurs by both minimizing the modulated capacitance seen by the voltage-controlled oscillator (VCO) tank and by reducing the duty cycle of the sampling clock. A 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> RF-dividerless frequency-tracking loop is also introduced to lock the CSPLL robustly when the VCO faces a sudden frequency disturbance. Fabricated in a 40-nm CMOS process, the prototype CSPLL occupies a core area of 0.13 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and synthesizes 9.6-to-12-GHz tones using a 100-MHz reference. At 11.2 GHz, it achieves a reference spur of −77.3 dBc and an RMS jitter of 48.6 fs while consuming 5 mW.

A 2.7-Gb/s CDR Circuit Based on Multiplexed Recirculating Delay-Locked Loop for ±10%-SSC Clock-Embedded Display Interface

A clock and data recovery (CDR) circuit based on a multiphase multiplexed recirculating delay-locked loop (MRDLL) is presented for spread-spectrum-modulation clock-embedded display interface. In the training stage, the MRDLL CDR is acting as a phase-locked loop (PLL) to generate sampling clocks. After the PLL is locked, the MRDLL CDR operates as a recirculating DLL to recover the incoming data. Implemented in the 90-nm CMOS process, the chip active area of the proposed MRDLL CDR is 0.118 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . As a 2.7-Gb/s spread-spectrum signal of 200-kHz modulation frequency and ±10% modulation depth with a triangular-shape frequency modulation is applied, the measured root-mean-square jitter of recovered data and clock is 9.27 and 4.03 ps, respectively. The power consumption is 5.23 mW.

Fully Digital On-Chip Wideband Background Calibration for Channel Mismatches in Time-Interleaved Time-Based ADCs

This letter presents a fully integrated on-chip digital mismatch compensation system for time-based time-interleaved (TI) data converters. The proposed digital compensation features blind calibration of gain, offset, and timing mismatches. The implemented system uses time-based sampling clock mismatch detection, achieving convergence within 32K samples, which is on par with analog-assisted background methods. A specialized filter structure compensates for timing mismatches of magnitude up to 0.21 of the sampling period, nearly triple the range of other published digital compensation methods, and is effective for input signals up to 0.92 Nyquist bandwidth. The on-chip digital correction achieves suppression of all mismatch tones to levels below −60 dBc while running fully in the background. The operation is demonstrated with an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> TI 2-GS/s analog-to-digital converter (ADC) prototype chip implemented in a 28-nm CMOS process.

Timing Jitter Analysis and Mitigation in Hybrid OFDM-DFMA PONs

Hybrid orthogonal frequency division multiplexing-digital filter multiple access passive optical networks (OFDM-DFMA PONs) offer a cost-effective solution to the challenging requirements of next-generation optical access networks and 5G and beyond radio access networks. It is crucial to consider the impact of timing jitter in any ADC/DAC-based system, therefore this paper presents an in-depth investigation into the impacts of DAC/ADC timing jitter on the hybrid OFDM-DFMA PON's performance. We introduce improved accuracy white and coloured, DAC and ADC timing jitter models, applicable to any DSP-based transmission system. We prove that DAC and ADC timing jitter effects are virtually identical and investigate the effects of white/coloured timing jitter on upstream performance in hybrid OFDM-DFMA PONs and determine the associated jitter-induced optical power penalties. To mitigate against the timing jitter-induced performance degradations, a simple, but highly effective DSP-based technique is implemented which increases robustness against the timing jitter effects and significantly reduces timing jitter-induced optical power penalties. This consequently relaxes DAC/ADC sampling clock jitter requirements and so reduces implementation costs. White (coloured) timing jitter effects are shown to be independent of (dependent on) ONU operating frequency band and a trade-off between DAC and ADC jitter levels can be exploited to reduce ONU costs.

Near-zero phase-lag hyperscanning in a novel wireless EEG system

Objective. Hyperscanning is an emerging technology that concurrently scans the neural dynamics of multiple individuals to study interpersonal interactions. In particular, hyperscanning with electroencephalography (EEG) is increasingly popular owing to its mobility and its ability to allow studying social interactions in naturalistic settings at the millisecond scale. Approach. To align multiple EEG time series with sophisticated event markers in a single time domain, a precise and unified timestamp is required for stream synchronization. This study proposes a clock-synchronized method that uses a custom-made RJ45 cable to coordinate the sampling between wireless EEG amplifiers to prevent incorrect estimation of interbrain connectivity due to asynchronous sampling. In this method, analog-to-digital converters are driven by the same sampling clock. Additionally, two clock-synchronized amplifiers leverage additional radio frequency channels to keep the counter of their receiving dongles updated, which guarantees that binding event markers received by the dongle with the EEG time series have the correct timestamp. Main results. The results of two simulation experiments and one video gaming experiment reveal that the proposed method ensures synchronous sampling in a system with multiple EEG devices, achieving near-zero phase lag and negligible amplitude difference between the signals. Significance. According to all of the signal-similarity metrics, the suggested method is a promising option for wireless EEG hyperscanning and can be utilized to precisely assess the interbrain couplings underlying social-interaction behaviors.