A fully integrated fast transient response digital low-dropout regulator with built-in sampling clock

Abstract

A fast transient digital low-dropout regulator (LDO), in which the sampling clock is adaptively generated by a voltage-controlled oscillator, is proposed in this paper. In steady state, the LDO operates at a fine-regulation mode and the oscillator generates a low-frequency clock for low power consumption. When the output voltage exceeds the boundaries of overshoot or undershoot, the LDO switches into a coarse-regulation mode with a higher clock frequency and a shorter response time. To enhance the transient performance at near-threshold region, a three-stage high-speed comparator is further introduced. The designed digital LDO was fabricated in standard 180 nm CMOS process. Measured results show that the maximum variation of transient output voltage is 120 mV while the load steps from 2 to 22 m A with a 10 ns edge time. The proposed LDO obtains a low quiescent current of 14.5 μA with a 0.0587 ps figure of merit.