RISC Processor Research Articles

Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V

With the proliferation of electronic devices, third-party intellectual property (3PIP) integration in the supply chain of the semiconductor industry and untrusted actors/fields have raised hardware security concerns that enable potential attacks, such as unauthorized access to data, fault injection and privacy invasion. Different security techniques have been proposed to provide resilience to secure devices from potential vulnerabilities; however, no one technique can be applied as an overarching solution. We propose an integrated Information Flow Tracking (IFT) technique to enable runtime security to protect system integrity by tracking the flow of data from untrusted communication channels. Existing hardware-based IFT schemes are either fine-, which are resource-intensive, or coarse-grained models, which have minimal precision logic, providing either control-flow or data-flow integrity. No current security model provides multi-granularity due to the difficulty in balancing both the flexibility and hardware overheads at the same time. This study proposes a multi-level granularity IFT model that integrates a hardware-based IFT technique with a gate-level-based IFT (GLIFT) technique, along with flexibility, for better precision and assessments. Translation from the instruction level to the data level is based on module instantiation with security-critical data for accurate information flow behaviors without any false conservative flows. A simulation-based IFT model is demonstrated, which translates the architecture-specific extensions into a compiler-specific simulation model with toolchain extensions for Reduced Instruction Set Architecture (RISC-V) to verify the security extensions. This approach provides better precision logic by enhancing the tagged mechanism with 1-bit tags and implementing an optimized shadow logic that eliminates the area overhead by tracking the data for only security-critical modules.

Design, development and testing of a 16-bit reduced instruction set computer architecture based processor

Design, development and testing of a 16-bit reduced instruction set computer architecture based processor

Development of floating point operating devices

The paper shows a well-known approach to the construction of cores in multi-core microprocessors, which is based on the application of a data flow graph-driven calculation model. The architecture of such kernels is based on the application of the reduced instruction set level data flow model proposed by Yale Patt. The object of research is a model of calculations based on data flow management in a multi-core microprocessor. The results of the floating-point multiplier development that can be dynamically reconfigured to handle five different formats of floating-point operands and an approach to the construction of an operating device for addition-subtraction of a sequence of floating-point numbers are presented, for which the law of associativity is fulfilled without additional programming complications. On the basis of the developed circuit of the floating-point multiplier, it is possible to implement various variants of the high-speed multiplier with both fixed and floating points, which may find commercial application. By adding memory elements to each of the multiplier segments, it is possible to get options for building very fast pipeline multipliers. The multiplier scheme has a limitation: the exponent is not evaluated for denormalized operands, but the standard for floating-point arithmetic does not require that denormalized operands be handled. In such cases, the multiplier packs infinity as the result. The implementation of an inter-core operating device of a floating-point adder-subtractor can be considered as a new approach to the practical solution of dynamic planning tasks when performing addition-subtraction operations within the framework of a multi-core microprocessor. The limitations of its implementation are related to the large amount of hardware costs required for implementation. To assess this complexity, an assessment of the value of the bits of its main blocks for various formats of representing floating-point numbers, in accordance with the floating-point standard, was carried out.

RISC processor implementation 32-bit MIPS-based: an approach to teaching and learning

This article describes the development of the design of a processor based on the RISC architecture, taking the 32-bit MIPS microprocessor as a basis. The RISC architecture, which stands for Reduced Instruction Set Computer, is characterized by having a reduced instruction set, aiming to optimize the processor's overall performance. The designed MIPS processor follows a 5-stage pipeline, which comprises the instruction fetch, instruction decode, execution, preparation and memory access phases. The main objective of this article is to carry out the structural development of the processor, using the hardware description language. This implies the creation of a Verilog representation that will later be used to generate the extraction of the processor's logic circuit. Furthermore, the project involves generating a timing diagram that illustrates the temporal behavior of processor operations and, ultimately, the physical implementation of the processor core. This work seeks to contribute knowledge in the field of computer architecture, providing a practical implementation of a RISC processor based on the 32-bit MIPS architecture, which can be relevant both for educational purposes and for practical applications in embedded systems.

Temperature response TADF/ RTP dual mode afterglow of carbon dots and flake C3N4 composites for information encryption and advanced lighting

TADF emission based on CD materials has inspired extensive attention in recent years. Herein, CD composites with afterglow color temperature-responsive were prepared by confining BCDs/ BPCDs in a g-C3N4 matrix. The covalent bonds extensively protect the triplet states and promote the ISC process, and the small △EST is sufficient to encourage the RISC process. At room temperature, the BCD composite exhibits a deep blue TADF emission, and the BPCD composite shows two TADF emission peaks in the blue-green region. BCD/ BPCD composites exhibit RTP emission at lower temperatures, and the competition between TADF and RTP leads to the color temperature-responsive properties in these composites. A simple concept of information encryption was developed to demonstrate the great potential of these composites in advanced security applications. Based on the high overall quantum yields (44 %) and broad full width at half maximum (over 140 nm) at the visible region of the BPCD composites, they are successfully applied to develop the single component fluorescence/ TADF dual-emission delay WLED with CIE coordinates and CRI of (0.32, 0.34) and 92. This work provides a new strategy for producing CDs-based TADF materials and may motivate CDs TADF materials applied in information encryption and advanced lighting application.

Modernized Resonant Column and Torsional Shearing Apparatus With Multipoint Contactless Displacement Detection System

Abstract In this study, a modification of resonant column/torsional shearing (RC/TS) apparatus was proposed to perform a qualitative analysis of a noncohesive soil specimen vibration during RC tests. An additional multipoint displacement detection system was installed in the RC/TS WF8500 device. In the new measuring system, 48 mini-magnets are attached to the side surface of a cylindrical soil specimen, creating a regular grid of measuring points. Around 48 Hall sensors (Honeywell SS495A1) are used to measure changes in the magnetic field strength due to the movement of the corresponding magnets on the surface of the specimen subjected to dynamic torque. The Hall sensor generates an analog signal that is proportional to the change in the magnetic field. The measurements are collected with a newly developed data acquisition system that consists of a set of analog-to-digital converters and a set of ARM (Advanced RISC (Reduced Instruction Sets Computing) Machine) microcontrollers. The measurement system is controlled with a dedicated software, ControlRec, developed by the authors. The measurements are taken synchronically with and independently from the standard RC test procedure. The new measuring technique allows to observe displacements of the 48 points on the specimens’ surface with over 4 times higher sampling rate than in the original measuring system. As a result, additional effects related to the mechanical wave propagation through soil specimen were observed (local disturbances in distribution of vibration amplitudes or significant displacements near the bottom end of the specimen, which is assumed to be fixed in the standard RC/TS results analysis), that could not be identified using the standard equipment of the device.

Laser Voltage Probing Attack Detection With 100% Area/Time Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design

In this work, a detection scheme signaling the occurrence of laser voltage probing (LVP) attacks in digital designs (e.g., cryptographic circuits) is introduced. The scheme comprises a standard cell-based photosensor fabric and distributed detectors. By construction, the scheme conforms the standard cell design discipline, restricted layout design rules, and commercial place and route tools. This allows seamless integration with automated design flows, and immediate adoption in a design-agnostic fashion. Hundred percentage time and area coverage is achieved for full protection against LVP attacks, while not requiring any calibration. Extensive attacks with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim $</tex-math> </inline-formula> 150 h of characterization with a state-of-the-art LVP equipment on a 28-nm testchip demonstrate laser detection at both above-and below-bandgap wavelengths and, hence, even at the very low electron-hole pair generation rate of the former ones. Attacks to an advanced encryption standard (AES) core are shown to be flagged at any practical laser intensity and best-in-class true 220-nm laser spot. Low circuit activity confines its power to leakage, amounting to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt;$</tex-math> </inline-formula> 0.1% of the AES power. At the worst case, 150% area overhead is substantially lower in practical cases where the information-sensitive blocks are a portion of it (e.g., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt;$</tex-math> </inline-formula> 20% in an advanced reduced instruction set computer machines (ARM) Cortex-M4 processor with a secure AES accelerator). To the best of the authors’ knowledge, this is the first demonstration of a design-agnostic on-chip protection against LVP attacks with full-area coverage under unmodified manufacturing/packaging process.

Design of Double 16_32 –Bit RISC Processor

Abstract: The SOCs built today offer a high level of functionality, serve a variety of applications, and improve in efficiency and cost. Embedded systems also face area and power consumption constraints in addition to real-time challenges. The main objective is to design and implement a 32-bit High-performance RISC (Reduced Instruction Set Computer) Processor architecture. The Processor is designed as an instantiation of submodules using Verilog HDL (Hardware Description Language). a 16-bit compatibility is introduced which makes use of the ISA to execute two 16bit operations at the same time and thus provides the capability to switch and execute both 32-bit and two 16-bit operations using the execution unit. The ISA is modified to meet the requirement to execute both 16-bit operation and 32-bit operations. Each of these instructions are independent of the other instruction and can be executed simultaneously. This enables the RISC based architecture to also enhance the speed of the design by a factor of 2 for 16 bit operations.

BASALISC: Programmable Hardware Accelerator for BGV Fully Homomorphic Encryption

Fully Homomorphic Encryption (FHE) allows for secure computation on encrypted data. Unfortunately, huge memory size, computational cost and bandwidth requirements limit its practicality. We present BASALISC, an architecture family of hardware accelerators that aims to substantially accelerate FHE computations in the cloud. BASALISC is the first to implement the BGV scheme with fully-packed bootstrapping – the noise removal capability necessary for arbitrary-depth computation. It supports a customized version of bootstrapping that can be instantiated with hardware multipliers optimized for area and power.BASALISC is a three-abstraction-layer RISC architecture, designed for a 1 GHz ASIC implementation and underway toward 150mm2 die tape-out in a 12nm GF process. BASALISC’s four-layer memory hierarchy includes a two-dimensional conflict-free inner memory layer that enables 32 Tb/s radix-256 NTT computations without pipeline stalls. Its conflict-resolution permutation hardware is generalized and re-used to compute BGV automorphisms without throughput penalty. BASALISC also has a custom multiply-accumulate unit to accelerate BGV key switching.The BASALISC toolchain comprises a custom compiler and a joint performance and correctness simulator. To evaluate BASALISC, we study its physical realizability, emulate and formally verify its core functional units, and we study its performance on a set of benchmarks. Simulation results show a speedup of more than 5,000× over HElib – a popular software FHE library.

High-Performance Hot-Exciton OLEDs via Fully Harvesting Triplet Excited States from Both the Exciplex Co-Host and the TBRb Emitter.

The high-level reverse intersystem crossing (HL-RISC, T2 → S1 ) process from triplet to singlet exciton, namely the "hot exciton" channel, has recently been demonstrated in the traditional fluorescent emitter of TBRb. Although it is a potential pathway to improve the utilization of non-radiative triplet exciton energy, highly efficient fluorescent organic light emitting diodes (FOLEDs) based on this "hot exciton" channel have not been developed. Herein, high-efficiency and low-efficiency roll-off FOLEDs are achieved through doping TBRb molecules into an energy-level matched exciplex co-host. Combining the low-level RISC (LL-RISC, EX3 → EX1 ) process in the exciplex co-host with the HL-RISC process of hot excitons in TBRb to fully harvest the triplet energy, a record-high external quantum efficiency (EQE) of 20.4% is obtained via a proper Dexter energy transfer of triplet excitons, realizing the efficiency breakthrough from fully fluorescent material-based OLEDs with TBRb as an end emitter. Furthermore, the fingerprint Magneto-electroluminescence (MEL) as a sensitive measuring tool is employed to visualize the "hot exciton" channel in TBRb, which also directly verifies the effective energy confinement and the full utilization of hot excitons. Obviously, this work paves a promising way for further fabricating high-efficiency TBRb-based FOLEDs for lighting and flat-panel display applications.

MF-RALU: design of an efficient multi-functional reversible arithmetic and logic unit for processor design on the field programmable gate array platform

Most modern computer applications use reversible logic gates to solve power dissipation issues. This manuscript uses an efficient multi-functional reversible arithmetic and logical unit (MF-RALU) to perform 30 operations. The 32-bit MF-RALU includes arithmetic, logical, complement, shifters, multiplexers, different adders, and multipliers. The multi-bit reversible multiplexers are used to construct the MF-RALU structure. The Reduced instruction set computer (RISC) processor is designed to realize the functionality of the MF-RALU. The MF-RALU can perform its operation in a single clock cycle. The 1-bit RALU is developed and compared with existing approaches with improvements in performance metrics. The 32-bit reversible arithmetic units (RAUs) and reversible logical units (RLUs) are constructed using 1-bit RALU. The MF-RALU and RISC processor are synthesized individually in the Vivado environment using Verilog-HDL and implemented on Artix-7 field programmable gate array (FPGA). The MF-RALU utilizes a &amp;lt;11% chip area and consumes 332 mW total power. The RISC processor utilizes a &amp;lt;3% chip area and works at 483 MHZ frequency by consuming 159 mW of total power on Artix-7 FPGA.

TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge

Extreme edge devices or Internet-of-Things (IoT) nodes require both ultra-low power (ULP) always-on (AON) processing as well as the ability to do on-demand sampling and processing. Moreover, support for IoT applications, such as voice recognition, machine monitoring, and so on, requires the ability to execute a wide range of machine learning (ML) workloads. This brings challenges in hardware (HW) design to build flexible processors operating in ULP regime. This article presents TinyVers, a tiny versatile ULP ML system-on-chip (SoC) to enable enhanced intelligence at the extreme edge. TinyVers exploits dataflow reconfiguration to enable multi-modal support and aggressive on-chip power management for duty cycling to enable smart sensing applications. The SoC combines an reduced instruction set computer-V (RISC-V) host processor, a 17-tera operations per second per watt (TOPS/W) dataflow reconfigurable ML accelerator, a 1.7- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W deep sleep wake-up controller (WuC), and an embedded magnetoresistive random access memory (eMRAM) for boot code and ML parameter retention. The SoC can perform up to 17.6 giga operations per second (GOPS) while achieving a power consumption range from 1.7 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W to 20 mW. Multiple ML workloads aimed for diverse applications are mapped on the SoC to showcase its flexibility and efficiency. All the models achieve 1–2 TOPS/W of energy efficiency with a power consumption below 230 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W in continuous operation. In a duty-cycling use case for machine monitoring, this power is reduced to below 10 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W.

Vectorization Programming Based on HR DSP Using SIMD

Single instruction multiple data (SIMD) vector extension has become an essential feature of high-performance processors. Architectures such as x86, ARM, MIPS, and PowerPC have specific vector extension instruction sets and SIMD micro-architectures. Using SIMD vectorization programming can significantly improve the performance of application algorithms while keeping the hardware overhead low. In addition, other methods can enhance algorithm performance, such as selecting the best SIMD vectorization model for algorithms, ensuring sufficient instruction streams, implementing reasonable and effective cache data prefetching, and aligning data access and storage addresses according to instruction characteristics. The goal of this paper is three-fold. First, we introduce the basic structural characteristics of a general RISC processor, Hua Rui (HR) DSP, with a custom vector instruction set based on compatibility with an MIPS64 fixed-point and floating-point instruction set, as well as a Fei Teng (FT) processor compatible with an ARMv8 instruction set. Second, we summarize the fundamental principles of SIMD vectorization programming design for the HR DSP, which provides ideas for other scholars or engineering and technical personnel to study the algorithm performance using SIMD vectorization optimization. Third, we implement representative typical algorithms based on the HR and FT platforms and obtain experimental results that show improvement in algorithm SIMD vectorization optimization according to the vector programming design principles summarized in this article can improve the single-core performance of scalar implementation without vectorization, instruction streams, and cache data prefetching by 4–22 times for mean filter, accumulation, and matrix–matrix multiplication, which is significantly better than the performance improvement of 3–13 times for the FT platform. Moreover, the performance of matrix–matrix multiplication using the best vectorization model on the HR platform is about 84% higher than that of the common SIMD vectorization model.

Design and Physical Synthesis of a 16 BIT RISC Processor

Design and Physical Synthesis of a 16 BIT RISC Processor

A novel reduced instruction set computer-communication processor design using field programmable gate array

In this paper, a novel reduced instruction set computer (RISC)- communication processor (RCP) has been designed with 32-bit operations which access 64-bit instruction format and implemented using field programmable gate array (FPGA). The design of the RISC processor is facilitated with communication operations like basic signals sine, cosine, and square, and modulation schemes like amplitude modulation, amplitude shift keying, analog, and digital quadrature amplitude modulation. Additionally, application-oriented operations like a traffic light, digital clock, and linear feedback shift register are included in the design. The pipeline mechanism is incorporated in the design to enhance the performance characteristics of the processor, hence allowing the execution of the instructions more effectively. Also, the design is implemented with Xilinx Virtex 7 family FPGA. The device utilization analysis of the proposed FPGA along with different FPGA families is evaluated and compared.

RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems

Magnetic random access memory (MRAM) is considered one of the most promising memories among nonvolatile memories (NVMs), to replace static random access memory (SRAM) in the computing system to improve its cache performance. In this article, performance evaluation and strategy exploration of three-level hybrid cache systems are conducted under the framework of Reduced InstrucTIon Set Computer-Five (RISC-V) instruction set. First, system-level joint calls of Nvsim, Gem5, McPAT, and other cache emulation architectures are implemented based on the system-level simulator called MAGPIE tool. Based on the performance comparison of spin transfer torque (STT)-MRAM, spin-orbit torque (SOT)-MRAM, and SRAM with varied capacities, a variety of combined CPU three-level hybrid cache architectures are simulated. The performances of the proposed hybrid cache systems and the bus impact of interconnecting are evaluated, with better analysis of the cost of CPU system implementation and interactions among levels of cache. The power consumption of different processors with various instruction sets and cores is also evaluated. It is demonstrated that SOT-MRAM and STT-MRAM show great potential applications as L2 and L3 caches in the RISC-V system. RISC-V shows the potential benefits for future CPU cache. Meanwhile, an adaptive stride prefetching strategy is proposed to address the problem of delay hysteresis and high miss rate of STT-MRAM in the L3 cache. The applicability of this strategy to different storage technologies and the comparison with cutting-edge technologies are also illustrated. Simulation results show that the prefetching strategy can achieve at most 64.12% and 94.55% optimization effects on the miss latency and the miss rate of L3 cache, respectively.

HIGHLY RECONFIGURABLE SOFT-CPU BASED PERIPHERAL MODULES DESIGN

Research motivation. When developing microcontrollers, manufacturers try to include as many different types of peripherals as possible in order to increase the marketing attractiveness of their products. On the one hand, with a large assortment of various peripheral modules, it is very difficult to implement several devices of the same type in the microcontroller: manufacturers are mainly limited to 1-2 instances, in rare cases 4 modules of the same type are included. On the other hand, most software projects do not use all the peripherals of modern microcontrollers and many devices are left unused, while there may be a shortage of other types of modules. Another problem that has become especially noticeable for microcontrollers used in the field of IoT is the cryptographic protection of data that is transmitted through built-in information exchange interfaces. The main efforts of researchers and developers of cryptographic data protection methods were aimed at reducing energy-intensive operations, memory access iterations and speeding up encryption processes while maintaining a high level of cryptographic protection and enabling efficient data distribution within IoT devices networks. Research results. This paper presents an alternative approach to the manufacture of peripheral modules as part of microcontrollers. The authors propose to use a configurable software processor module based on the MIPS architecture with a reduced instruction set and limited capabilities. Conclusions. This approach would make it possible to dynamically change the functionality of peripheral modules in accordance with the requirements of the developed software solution, which in turn will increase the efficiency of the microcontroller chips capabilities utilization. In addition, the transfer of data stream encryption functions to the reconfigurable core of the peripheral module will provide fast and transparent cryptographic protection, as well as allow offloading the microcontroller core and increasing the energy efficiency of chips while reducing their production cost.

Theoretical study of the solid-state effect on red hot excitons combined with aggregation induced emission molecule

In this study, we have theoretically investigated the solid-state effects of three molecules that combine the hot exciton and AIE mechanisms. The results show that the AIE effect is verified by the decreased H-R factor of the molecule in the solid phase due to the RIR effect.TPAPHOC2 has stronger intermolecular interactions in the solid phase and its fluorescence quantum yield is more different from that in solution. The molecules have smaller ΔES1-T2 and larger SOC in thin films, which promotes the RISC process. The study well explains the experimental results and provides insights into the molecular design.

Basic RISC-V Instruction Set Architecture: Design and Validation

Abstract: This project's primary goal is to design and implement a simple RISC V instruction set architecture. This paper offers insights into the architecture of the risc v instruction set. This system employs the RISC V R-type (register) type instruction format. Using this format, we designed the fundamental isa and tested its functionality using verilog code. There is no licence fee for using RISC V, an open source isa that is available to everyone. Reduced instruction set (RISC) computers are created to make the individual instructions given to computers to perform various tasks more manageable. Most instruction set architectures, or isas, are proprietary and cannot be used or modified without permission from the companies; as a result, an isa that is free and open source, which is provided by risc v, will help in increasing the speed and lowering system costs by using these instruction set formats, and we are designing 32 bit isa architecture. instruction formats for the risc v instruction set architecture

Innate immune regulations and various siRNA modalities.

RNAi therapeutics are designed to produce the precise silencing effects against the gene-linked diseases which were known to be untreatable in the past. The highly immunostimulatory nature of siRNA enhances the off-target effects and easily get attacked by nucleases; hence, their modulation is essentially required for accurate alterations to be made in the structures to intensify the pharmacological attributes. The phosphonate modifications act as shield against undue phosphorylation effects, and the molecular changes in ribose sugar lowers the level of immunogenicity and increases the binding efficacy. When bases are substituted with virtual/or pseudo bases, they eventually reduce the off-target effects. These changes modulate the nucleic acid sensors and control the hyper-activation of innate immune response. Various modification designs based on STC (universal pattern), ESC, ESC + (advanced patterns) and disubstrate have been explored to silence the gene expression of various diseases e.g., hepatitis, HIV, influenza, RSV, CNV and acute kidney injury. This review describes the various innovative siRNA therapeutics and their implications on the developed immune regulations to silence the disease effects. siRNA causes the silencing effects through RISC processing. The innate immune signalling is induced by both TLR-dependent and TLR-independent pathways. Modification chemistries are utilized to modulate the immune response.