Design of Double 16_32 –Bit RISC Processor

Abstract

Abstract: The SOCs built today offer a high level of functionality, serve a variety of applications, and improve in efficiency and cost. Embedded systems also face area and power consumption constraints in addition to real-time challenges. The main objective is to design and implement a 32-bit High-performance RISC (Reduced Instruction Set Computer) Processor architecture. The Processor is designed as an instantiation of submodules using Verilog HDL (Hardware Description Language). a 16-bit compatibility is introduced which makes use of the ISA to execute two 16bit operations at the same time and thus provides the capability to switch and execute both 32-bit and two 16-bit operations using the execution unit. The ISA is modified to meet the requirement to execute both 16-bit operation and 32-bit operations. Each of these instructions are independent of the other instruction and can be executed simultaneously. This enables the RISC based architecture to also enhance the speed of the design by a factor of 2 for 16 bit operations.