Laser Voltage Probing Attack Detection With 100% Area/Time Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design

Abstract

In this work, a detection scheme signaling the occurrence of laser voltage probing (LVP) attacks in digital designs (e.g., cryptographic circuits) is introduced. The scheme comprises a standard cell-based photosensor fabric and distributed detectors. By construction, the scheme conforms the standard cell design discipline, restricted layout design rules, and commercial place and route tools. This allows seamless integration with automated design flows, and immediate adoption in a design-agnostic fashion. Hundred percentage time and area coverage is achieved for full protection against LVP attacks, while not requiring any calibration. Extensive attacks with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim $</tex-math> </inline-formula> 150 h of characterization with a state-of-the-art LVP equipment on a 28-nm testchip demonstrate laser detection at both above-and below-bandgap wavelengths and, hence, even at the very low electron-hole pair generation rate of the former ones. Attacks to an advanced encryption standard (AES) core are shown to be flagged at any practical laser intensity and best-in-class true 220-nm laser spot. Low circuit activity confines its power to leakage, amounting to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt;$</tex-math> </inline-formula> 0.1% of the AES power. At the worst case, 150% area overhead is substantially lower in practical cases where the information-sensitive blocks are a portion of it (e.g., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt;$</tex-math> </inline-formula> 20% in an advanced reduced instruction set computer machines (ARM) Cortex-M4 processor with a secure AES accelerator). To the best of the authors’ knowledge, this is the first demonstration of a design-agnostic on-chip protection against LVP attacks with full-area coverage under unmodified manufacturing/packaging process.