Ripple Cancellation Technique Research Articles

A low dropout regulator design with 20.4 μA quiescent current and high power supply rejection

This paper presents a novel low dropout (LDO) regulator distinguished by its high power supply rejection (PSR) and low quiescent current. A capacitive feed-forward ripple cancellation (CFFRC) technique is introduced to effectively cancel power supply noise while simultaneously minimizing quiescent current. Additionally, the design incorporates feed-forward capacitors and back-to-back pseudo-resistors biasing to achieve reduced power consumption. Furthermore, the integration of negative feedback super source follower and Miller compensation techniques enhances the stability of the LDO. Fabricated using 180 nm CMOS technology, the LDO exhibits a quiescent current consumption of 20.4 μA. Experimental results demonstrate a maximal improvement of −41.55 dB in PSR compared to an LDO lacking these enhancements, with a maximum load current capability of 120 mA.

A High-PSRR NMOS LDO Regulator With Intrinsic Gain-Tracking Ripple Cancellation Technique

A High-PSRR NMOS LDO Regulator With Intrinsic Gain-Tracking Ripple Cancellation Technique

A 0.9-μA Quiescent Current High PSRR Low Dropout Regulator Using a Capacitive Feed-Forward Ripple Cancellation Technique

This article presents a high power supply rejection ratio (PSRR) low dropout (LDO) regulator with a low quiescent current. A low quiescent current capacitive feed-forward ripple cancellation (CFFRC) technique is proposed to cancel the power supply noise. With this technique, low power consumption is achieved via feed-forward capacitors and back-to-back pseudo-resistors bias. This design was fabricated using the 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology. The entire proposed LDO consumes a quiescent current of 0.9 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> . Compared with an LDO without enhancement, at the maximum load current of 200 mA, the measured PSRR has an enhancement of −22 dB at 1 MHz.

A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation

This work presents an always-on reference ripple cancellation technique that actively cancels the reference settling error throughout the entire SAR conversion process. Unlike the conventional designs that require high-speed reference buffers or large on-chip decoupling capacitors to minimize the error, it incorporates an extra path to actively cancel the error, which can provide considerable reference ripple tolerance, thus significantly relaxing the reference settling requirement. To verify the proposed technique, a prototype 10-bit 100-MS/s SAR ADC is fabricated in a 40-nm CMOS process. Equipped with the proposed technique, it only requires a 0.5-pF decoupling capacitor and an on-chip low-power reference buffer consuming 0.26-mW static power. The proposed technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL) and differential non-linearity (DNL) by 15 times. Overall, the prototype ADC achieves an SNDR of 56.3 dB at Nyquist rate while consuming 1.4 mW, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">including</i> on-chip reference buffers.

A flicker-free decoupled ripple cancellation technique for LED driver circuits

Light-emitting diode (LEDs) even though are the major lighting source, they suffer from flickering which has adverse effects on human health. With this wide increase in usage, more focus has been on minimizing the ripples, which is the root cause of flickers in LED driver circuits. Initial solution of electrolytic capacitor suffers from shorter lifetime, bulky weight, and high risk of fault. In this regard, a series current ripple cancellation (RC) technique has been proposed in this paper for flicker free operation. The key features of the proposed RC method include unity power factor (UPF) at source end, simple control, and reduced smoothing capacitance value. The proposed system has been validated in both MATLAB/Simulink environment and experimental investigations. Further, detailed analysis and comparative evaluation with the state-of-the-art work reported in the literature has been presented.

High-PSRR Low-dropout Regulator with Fast Transient Response Time and Low Output Peak Voltage

This study proposes the feed-forward ripple cancellation (FFRC) technique to low drop-out (LDO) regulator. By adding load tracking impedance to the gate of pass transistor, it is possible to secure stability with a 100-nF capacitor having low ESR and be obtained less than 35 ㎱ response time. In all frequency bands, a power supply rejection ratio (PSRR) less than -70 ㏈ is obtained when the load current is 10 ㎃. The circuit is implemented in 65-㎚ CMOS process.

Frequency Stabilization and EMI Noise Reduction of COT Method Ripple-Controlled Switching Converters with Output Voltage Ripple Cancellation

This paper proposes a new EMI reduction and automatic ripple cancellation technique about the ripple-controlled converter with the ripple injection and Constant-On Time (COT) method. The ripple-controlled converters have no stable clock and it is difficult to reduce the EMI noise by shaking the operating frequency. The new method of EMI reduction is that the COT pulse width is modulated by the triangular signal so that the operating frequency is modulated and the spectrum peak level of the clock frequency is greatly reduced. But the output voltage ripple is much increased because of the change of the duty ratio of the operating frequency. The increaced ripple is canceled by adding the modulation signal to the ripple injection circuit. Moreover stabiliztion of the operating frequency on Discontinuous Conduction Mode (DCM) is reported. The operating frequency falls down on DCM mode in the COT converters. To stabilize the operating frequency, cheking the operating period is fedback to control the COT pulse width

LED driver based on novel ripple cancellation technique for flicker‐free operation and reduced power processing

Light-emitting-diode (LED) drivers are required to maintain the power quality of both the AC input and DC output side. The regulation prevents adverse impacts on the grid and maintains the nominal operating condition of LEDs. Without significant filtering, the input power from a single-phase AC source can result in low-frequency flickers that raise health issues. This study proposes a LED driver topology to achieve low harmonics at the AC side and maintain flicker-free operation to drive LEDs. A novel ripple-cancelling scheme is developed to minimise redundant power processing and reduce circuit complexity to achieve high-conversion efficiency. The new topology supports a simple control strategy to operate the driver effectively. Experimental evaluation demonstrates the system performance and verifies the novelty and contribution.

A Low-Dropout Regulator with PSRR Enhancement through Feed-Forward Ripple Cancellation Technique in 65 nm CMOS Process

In this paper, a low-dropout (LDO) regulator with an enhanced power supply rejection ratio (PSRR) is proposed with a feed-forward ripple cancellation technique (FFRC) in 65 nm CMOS technology. This technique significantly improves the PSRR over a wide range of frequencies, compared to a conventional LDO regulator. The LDO regulator provides 35–76.8 dB of PSRR in the range of 1 MHz–1 GHz, which shows up to 30 dB of PSRR improvement, compared with that of the conventional LDO regulator. The implemented LDO regulator has a dropout voltage of 0.22 V and a maximum load current of 20 mA. It can also provide an output voltage of 0.98 V at a range of 1–1.3 V of the input voltage. The load regulation is 2.3 mV/mA while the line regulation is 0.05 V/V. The circuit consumes 385 μA with an input voltage of 1.2 V. The total area without pads is 0.092 mm2.

Research on low input current ripple two‐stage converter for low frequency pulsed‐power applications

In this study, a two-stage cascaded pulsed power converter based on the proposed optimised control scheme has been presented. In order to eliminate the low-frequency input current ripple, the front-stage converter only needs to provide average power and the second-stage converter provides pulsed power. Meanwhile, the isolation of energy transfer mode combines with the proposed optimised control method based on the input current AC signal feedback control guarantee smooth input power with low repeat frequency pulsed load. To demonstrated the effectiveness of the proposed low-frequency input current ripple cancellation technique, a 1 kW peak pulsed power prototype is built and tested. The experimental results verify the validity and reliability of the two-stage isolated pulsed power converter with proposed optimised control method, and the proposed methods and concepts in this study can also be applied to all kinds of pulsed power applications.

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique

This article presents a reference ripple cancellation technique for high-speed successive approximation register analog-to-digital converters (SAR ADCs) to address the reference voltage settling issue. Unlike prior techniques that aim to minimize the reference ripple, this article proposes a new perspective: it provides an extra path for the full-sized reference ripple to couple to the comparator but with an opposite polarity, so that the effect of the reference ripple is canceled out, thus ensuring an accurate conversion result. To verify the proposed technique, a prototype 10-bit 120-MS/s SAR ADC is fabricated in a 40-nm CMOS process. The proposed ripple cancellation technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL)/differential non-linearity (DNL) by ten times. Overall, the ADC achieves an SNDR of 55 dB with only 3-pF reference decoupling capacitor.

A 65-nm CMOS Low Dropout Regulator Featuring &gt;60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range

One of the most critical attributes of low dropout regulators (LDOs) in increasingly complex systems on chip (SoCs) is high-power supply rejection ratio (PSRR), not only over a wide frequency range but also over a large load current range. This paper presents an LDO, realized in 65-nm CMOS, featuring >60-dB PSRR over a 10-MHz frequency range and a 100-mA large load current range. The high PSRR is achieved by an adaptive feed forward ripple cancellation (FFRC) technique embodying an adaptive load current tracking scheme. By means of embodying an NMOS-based power stage, the LDO also achieves very low dropout voltage of 80 mV and features very small overshoot and undershoot of 2 and 4 mV, respectively.

A Passive Filter Building Block for Input or Output Current Ripple Cancellation in a Power Converter

This paper analyzes a coupled inductor based $LL$ – $LC$ network as a building block to achieve input or output current ripple cancellation in power converters. The proposed current ripple cancellation technique works on the principle of inductance matching. It also provides reduced current stress on the switching devices of the converter compared with the other current ripple cancellation networks discussed in the literature. The current ripple cancellation technique is verified in achieving input and output current ripple minimization in different converters. The effect of inductance mismatch, inductor and capacitor tolerances, and circuit parasitic is also studied. Some of the published research works are demonstrated to be a special case of the proposed idea. The effectiveness of the proposed method is validated by demonstrating the zero-ripple input current using a 31 V dc to 60 V dc, 240 W boost converter prototype and a 31 V dc to 115 V (rms) ac, 320 W current-fed-switched inverter prototype, and the zero-ripple output current using a 62 V to 42 V dc, 450 W buck converter prototype.

Input Current Ripple Cancellation Technique for Boost Converter Using Tapped Inductor

This paper presents a boost converter with a proposed tapped inductor ripple cancellation network. Based on the conventional boost converter (CBC), a small capacitor and a small inductor are added as the ripple cancellation network (RCN) in the proposed converter. Meanwhile, the tapped inductor can be easily realized by adding an extra tap in the main inductor of the CBC. Since the capacitor and inductor in the RCN do not need to handle the main power as the conventional LC input filter, the size and weight of the proposed converter are relatively small comparing the CBC with the LC input filter. The small signal and dynamic characteristics analyses show that the proposed converter has the same static and dynamic responses as the CBC, and the input current ripple cancellation can be achieved in all power ranges without significantly increasing the losses. Finally, three 36-50-V, 500-W prototypes operating at 100 kHz are implemented to verify the expected performance. The simulation and experimental results show that the proposed converters can achieve input current ripple cancellation with efficiency higher than 97.4% in all power ranges.

The Ripple Cancellation Technique Applied to a Synchronous Buck Converter to Achieve a Very High Bandwidth and Very High Efficiency Envelope Amplifier

This paper presents a single-stage converter for a high-bandwidth and high-efficiency envelope amplifier. In the proposed application, due to the high peak-to-average-power ratio, high bandwidth, and the power level requirements, the envelope amplifier has low efficiency. Therefore, many efforts have been made to increase the efficiency of the envelope amplifier. To achieve this improvement, the current ripple cancellation technique is applied in this paper to a synchronous buck converter to cancel the output current ripple and to decrease the switching frequency without a reduction in the large signal bandwidth, for open-loop operation and for the envelope elimination and restoration technique. The advantages of the proposed design are presented and validated experimentally. The transfer function of the output filter of the buck converter with a ripple cancellation circuit has been modeled and compared to measurements, showing a good correspondence. Experimental validation is provided at 4 MHz of switching frequency, for dc and for variable output voltage, applying a sinusoidal reference and a 64-QAM signal. Experimental validation of the efficiency improvement is provided, compared to the equivalent design of the conventional buck converter in terms of the output voltage ripple rejection ratio and large signal bandwidth.

A low-voltage high PSR LDO regulator with a simple ripple cancellation technique

A low-voltage high PSR LDO regulator with a simple ripple cancellation technique

Active current ripple cancellation in parallel connected buck converter modules

Parallel connection of converters has become a popular method of improving efficiency. This study first presents a design technique for a buck converter with two parallelly connected power modules (PMs), where one PM is designed with large current ripple for high efficiency. This study then demonstrates an active current ripple cancellation technique, where the current waveform of the second PM is shaped to be the exact opposite to that in the first PM, to reduce the current ripple as seen by the output capacitor. The factors that affect the overall efficiency in a parallel connected converter and the calculation of the parameters that determine the effectiveness of the ripple cancellation are reported. A prototype parallel converter is designed based on the proposed converter design technique and the current ripple seen by the output capacitor is successfully reduced by 66% with the proposed ripple cancellation technique, under different line and load conditions.

High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique

A low drop-out (LDO) regulator with a feed-forward ripple cancellation (FFRC) technique is proposed in this paper. The FFRC-LDO achieves a high power-supply rejection (PSR) over a wide frequency range. Complete analysis and design steps of the FFRC-LDO are presented in this paper. Kelvin connection is also used to increase the gain-bandwidth of the LDO allowing for faster transient performance. The LDO is implemented in 0.13 ¿m CMOS technology and achieves a PSR better than - 56 dB up to 10 MHz for load currents up to 25 mA. Load regulation of 1.2 mV for a 25 mA step is measured, and the whole LDO consumes a quiescent current of 50 ¿A with a bandgap reference circuit included. To our knowledge, this is the first LDO that achieves such a high PSR up to 10 MHz.

Novel active ripple filter for the solar array shunt switching unit

This article introduces an inductor enhancement active filter for a pulse-width-mo dulated type sequential switching unit (SSU) for spacecraft applications. The SSU draws a pulsating current from the solar array, which must be suppressed with a large inductor to keep it below the specified electromagnetic interference level. This inductor adds significantly to the weight of the SSU. Instead, a much smaller inductor can be used and its effective inductance enhanced by employing the ripple cancellation technique. The amount of inductance enhancement is limited by the stability of the active compensation loop.