A 65-nm CMOS Low Dropout Regulator Featuring >60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range

Abstract

One of the most critical attributes of low dropout regulators (LDOs) in increasingly complex systems on chip (SoCs) is high-power supply rejection ratio (PSRR), not only over a wide frequency range but also over a large load current range. This paper presents an LDO, realized in 65-nm CMOS, featuring >60-dB PSRR over a 10-MHz frequency range and a 100-mA large load current range. The high PSRR is achieved by an adaptive feed forward ripple cancellation (FFRC) technique embodying an adaptive load current tracking scheme. By means of embodying an NMOS-based power stage, the LDO also achieves very low dropout voltage of 80 mV and features very small overshoot and undershoot of 2 and 4 mV, respectively.