A low dropout regulator design with 20.4 μA quiescent current and high power supply rejection

Abstract

This paper presents a novel low dropout (LDO) regulator distinguished by its high power supply rejection (PSR) and low quiescent current. A capacitive feed-forward ripple cancellation (CFFRC) technique is introduced to effectively cancel power supply noise while simultaneously minimizing quiescent current. Additionally, the design incorporates feed-forward capacitors and back-to-back pseudo-resistors biasing to achieve reduced power consumption. Furthermore, the integration of negative feedback super source follower and Miller compensation techniques enhances the stability of the LDO. Fabricated using 180 nm CMOS technology, the LDO exhibits a quiescent current consumption of 20.4 μA. Experimental results demonstrate a maximal improvement of −41.55 dB in PSR compared to an LDO lacking these enhancements, with a maximum load current capability of 120 mA.