Abstract
A high power supply rejection (PSR) low dropout (LDO) regulator is presented in the paper for system on chip applications. The small signal models of LDOs are analyzed and a power noise cancellation technique is developed. The PSR performance is improved by introducing a negative capacitor at the gate of power devices. The proposed technique is verified with an LDO that is simulated in a $0.18\mu \mathrm {m}$ CMOS technology with a power supply of 1. 2V. The entire LDO dissipate $76\mu A$ quiescent current. The PSR is better than -30dB for the 0.1MHz-l0MHz frequency range when delivering a current of l0mA.
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