Reverse Bias Safe Operating Area Research Articles

Robust reverse bias safe operating area and improved electrical performance in 3300 V non-proportionally scaled insulated gate bipolar transistors

Robustness under high-temperature clamped inductive turn-off has been compared systematically among 3300 V scaled insulated gate bipolar transistors (IGBTs) with scaling factor k from 1 to 10 by technology computer-aided design simulations. Degradation of the reverse bias safe operating area (RBSOA) has been observed in proportionally scaled IGBTs, especially at a high turn-off current density. A non-proportional scaling method has been proven to be able to restore the robustness degradation with RBSOA close to the original k = 1 case. Moreover, the method for adjusting R pf (P-floating connecting resistor) adds more flexibility to device design and also improves the overall electrical performance of non-proportionally scaled IGBTs. The adjustment of R pf has been found to have a minimal effect on the RBSOA.

Improvement in U-Shaped Channel SOI Lateral IGBT for Wider Reverse Bias Safe Operating Area

In this article, the inductive turn-off failure mechanism of U-shaped channel silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT) under high-voltage and high-current is investigated by experiments and numerical simulations. First, the measured turn-off waveforms before and after failure are compared to infer the cause of the failure. Then, the failure is reproduced by calibrated three-dimensional simulations using Sentaurus TCAD. According to the simulation and measured results, the turn-off failure is resulted from the high impact ionization in the bird’s beak region. To reveal the failure mechanism, the turn-off failure process is divided into two phases. In phase I, the electrons generated by drastic impact ionization in the bird’s beak region act as the base current to keep the operation of parasitic PNP transistor after channel pinching off. In phase II, the parasitic NPN transistor is activated due to the hole current amplified by PNP, and thus, turn-off failure occurs. Based on the revealed turn-off failure mechanism, an improved U-shaped channel SOI-LIGBT with a P-top is proposed. The P-top is arranged in the bird’s beak region to reduce the impact ionization rate. The measured results demonstrate that no failure occurs when the improved device turns off under high-voltage and high-current conditions. Compared with the conventional U-shaped channel SOI-LIGBT, the improved device obtains 275% and 23% improvements in turn-off current at a bus voltage of 450 V and reverse bias safe operation area, respectively.

Termination area design for reduced leakage current and improved ruggedness of HV IGBTs

Abstract A termination design which efficiently reduces leakage current and improves robustness of very high voltage insulated gate bipolar transistors (IGBTs) (>3.3 kV) without adversely affecting other device characteristics is presented here. Proposed design uses a selectively formed Buried N+ layer in the N-buffer under the termination region. Optimised placement of the N+ buried regions reduces carrier modulation in the termination area thus lowering the leakage current and reducing maximum temperature during the reverse bias safe operating area tests. This improves dynamic ruggedness of the IGBT without deteriorating other device characteristics.

The Effect of Circuit Parameters on Reverse Biased Safe Operating Area of SiC MOSFET

In recent years, silicon carbide (SiC) and other wide band gap semiconductors have become one of the strategic commanding heights in the global high-technology field. Silicon Carbide (SiC) metal-oxide-semiconductor field effect transistor (MOSFET) has shown excellent electrical properties. When applying SiC MOSFET, the safe operation area (SOA) need to be considered. In this paper, the effect of circuit parameters on RBSOA of SiC MOSFET is researched. Firstly, the principle of RBSOA is introduced. Secondly, the equivalent circuit of the single-pulse test circuit is shown to study on the effect of gate resistance and gate voltage on RBSOA. Thirdly, the simulation of variable parameters are done to research the variation trend. Finally, experiments are done to verify the results which can make an important influence on safe operation of SiC MOSFET and help choose suitable circuit parameters.

Effect of short circuit aging on safe operating area of SiC MOSFET

In this paper, we study the effect of aging of SIC MOSFETs on Short Circuit Safe Operating Area and Reverse Bias Safe Operating Area of SiC MOSFETs. SCSOA and RBSOA are determined using short circuit and unclamped inductive switching tests, respectively. Aging of SiC MOSFETs are performed with repetitive short circuit tests at low dissipated energies, which allows to validate the relevance of evolution of different aging indicators measured during the aging process. The decrease in the dissipated energy leading to failure in short circuit and unclamped inductive switching tests allows to clearly link the evolution of these Safe Operating Areas to the degradation of electrical performances (drain and gate leakage currents and on-state resistance). Obtained results show that a strong increase in the drain and/or gate leakage currents after aging has a great effect on the decrease of Safe Operating Area especially on RBSOA and that on-state resistance increase due to aging process represents less impacts in the evolution of RBSOA than in the case of SCSOA. It is also clear from the obtained results that without any apparent evolution of these leakage currents, the decrease of SCSOA after aging is related to the increase in the on-state resistance.

Characteristics of 600, 1200, and 3300 V Planar SiC-MOSFETs for Energy Conversion Applications

SiC-MOSFETs provide superior performance for next generation power electronics systems. High threshold voltage 600 V SiC-MOSFETs were realized utilizing a reoxidation process, which drastically improves a tradeoff between an ON-resistance and a threshold voltage. Low-loss SiC-MOSFETs with a 1200 V/100-A rating have been developed. Using the developed SiC-MOSFETs, 1200 V/800-A high-power full SiC module with an ON-resistance as low as 2.9 m $\Omega $ at 150 °C was successfully fabricated. The high-power module markedly reduces power loss especially at high carrier frequency. Large-area 3300 V SiC-MOSFETs with an ON-resistance of 52 m $\Omega $ at 175 °C exhibit an adequate reverse bias safe operating area and 3300 V SiC-MOSFETs screened by applying a body diode current stress show stable characteristics under a continuous current through their body diode for 1000 h.

Design and Characterization of High-Voltage Silicon Carbide Emitter Turn-off Thyristor

A novel MOS-controlled silicon carbide (SiC) thyristor device, the SiC emitter turn-off thyristor (ETO), as a promising technology for future high-voltage and high-frequency switching applications has been developed. The world's first 4.5-kV SiC p-type ETO prototype based on a 0.36 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SiC p-type gate turn-off (GTO) shows a forward voltage drop of 4.6 V at a current density of 25 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a turn-off energy loss of 9.88 mJ. The low loss shows that the SiC ETO could operate at a 4-kHz frequency with a conventional thermal management system. This frequency capability is about four times higher than the 4.5-kV-class silicon power devices. The numerical simulations and theoretical analysis have been carried out to show the potentially improved performance of the high-voltage SiC ETOs. The results show that the high-voltage (10-kV) SiC n-type ETO has much better tradeoff performance than that of the p-type ETO due to a smaller current gain of the lower bipolar transistor in the SiC n-type GTO. Further improvement of the 10-kV SiC n-type ETO can be made with the optimum design of the drift layer carrier lifetime and buffer layer doping concentration of the 10-kV SiC GTO. The theoretical analysis and numerical simulation shows the SiC ETO also has the excellent reverse bias safe operating area. The experimental and theoretical studies show that the SiC ETO is a promising candidate for high-voltage (> 5 kV) power conversion applications.

Design and Characterization of High-Voltage 4H-SiC p-IGBTs

High-voltage p-channel 4H-SiC insulated gate bipolar transistors (IGBTs) have been fabricated and characterized. The devices have a forward voltage drop of 7.2 V at 100 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a -16 V gate bias at 25degC, corresponding to a specific on-resistance of 72 mOmega ldr cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a differential on-resistance of 26 mmOmega ldr cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Hole mobility of 12 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V ldr s in the inversion channel with a threshold voltage of -6 V was achieved by optimizing the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> well doping profile and gate oxidation process. A novel current enhancement layer was adopted to reduce the JFET resistance and enhance conductivity modulation by improving hole current spreading and suppressing the electron current conduction through the top n-p-n transistor. Inductive switching results have shown that the p-IGBT exhibited a turn-off time of ~1 mus and a turn-off energy loss of 12 m J at 4-kV dc-link voltage and 6-A load current at 25degC. The turn-off trajectory from the measured inductive load switching waveforms and numerical simulations shows that the p-IGBT had a near-square reverse bias safe operating area. Numerical simulations have been conducted to achieve an improved tradeoff between forward voltage drop and switching off energy by investigating the effects of drift layer lifetime and p-buffer layer parameters. The advantages of SiC p-IGBTs, such as the potential of very low ON-state resistance, slightly positive temperature coefficient, high switching speed, small switching losses, and large safe operating area, make them suitable and attractive for high-power high-frequency applications.

Effect of a buffer layer in the epi-substrate region to boost the avalanche capability of a 100V Schottky diode

The aim of this paper is to give an insight and a possible explanation of the limitations in the Reverse Bias Safe Operating Area of 100V Si Power Schottky Diodes. Starting from experiments and going through device simulations and theory a physical explanation of device failure both in short (i.e. isothermal) and long pulse are explained. With the help of the theoretical analysis an improvement of the design is proposed to increase avalanche capability of these devices and preliminary experimental data are reporting a very promising increase of both the maximum sustainable current in avalanche condition and the maximum sustainable avalanche energy in UIS conditions.

New generation 1200 V power module with trench gate IGBT and super soft recovery diode and its evaluations

A 1200 V IGBT with trench gate and punch through structures is developed on the basis of simulation and experimental analyses. Both results of simulation and measurement of the prototype device have good agreement. Though the chip area of the new IGBT is about 30-50% smaller than that of the conventional IGBT, the saturation voltage is about 30-40% lower, the switching loss is also about 20%, smaller than those of conventional IGBT, respectively, and the new IGBT has a larger reverse bias safe operating area (RBSOA). Capability to withstand short circuits is achieved by a new current limiting circuit. In addition, a fast switching diode with an excellent soft recovery characteristic is practically developed by using local lifetime control processing in the anode side n-layer. As an experimental result, its power dissipation, spike surge voltage and electromagnetic noise can be lowered. The structures and characteristics of the developed IGBT, diode and power module are presented, and their analytical results are discussed and evaluated from a practical and an applications point of view.

Aspects of the Conductivity Modulation Enhancement Effect in a 4500 V Planar Metal Oxide Semiconductor Device and Its Electrical Characteristics

A new high-power (4500 V) planar metal oxide semiconductor (MOS) device is fabricated and its properties are evaluated. It has low forward voltage drop and a large reverse bias safe operating area (RBSOA), and allows easy MOS control. These properties are superior to those of the conventional insulated gate bipolar transistor (IGBT) and the gate turn-off thyristor (GTO). This is due to the conductivity modulation enhancement effect resulting from an extremely wide gate electrode, which increases the hole storage and the electron injection. At the same time, the junction field effect transistor (JFET) resistance effect does not affect the forward voltage drop. The rate of increase of the off-state voltage (dVD/dt) during the turn-off process affects RBSOA markedly, therefore, it is important to set the gate resistance to an appropriate value. The press pack device that includes 20 chips of this device and 10 fast recovery diode chips can turn off a current of 1200 A at 3600 V DC voltage supply without a snubber circuit.

A Simplified Spice Model for IGBT

A simplified IGBT (Insulated Gate Bipolar Transistor) SPICE macromodel, based on its equivalent circuit, is proposed. This macromodel is provided to simulate various mechanisms governing the behavior of the IGBT, and it takes into account specific phenomena limiting its SOA (Safe Operating Area), such as forward and reverse biased SOA, as well as latch-up. The validity of this model is confirmed by comparison between simulation and experimental results as well as the data sheets. This comparison is tested for two IGBT devices showing two different powers and switching speeds, and a good agreement is recorded for both IGBT devices.

Reverse biased safe operating area of emitter switched thyristors

The reverse biased safe operating area (RBSOA) of 600 V and 2500 V EST devices has been analyzed by numerical simulation for the first time and compared with those for the IGBT and MCT. The dependence of the RBSOA upon the P-base resistance in the main thyristor structure of the EST has also been investigated. Two types of destructive failure mechanisms have been identified: one due to the voltage-induced avalanche multiplication, and the other associated with current-induced latch-up of the parasitic thyristor. It is demonstrated that, although the voltage-induced limit is identical for all three devices, the current induced RBSOA for the EST can be improved over the IGBT and MCT with little sacrifice of the on-state characteristics. In addition, a comparison of the RBSOA with the forward biased safe operating area (FBSOA) has been performed.

RBSOA characterization of GTO devices

GTO devices are characterized using a nondestructive RBSOA (reverse-bias safe operating area) tester. Breakdown phenomena observed in GTO testing are very much different from those of a BJTs. Explanation of the cause of the loss of device voltage blocking capability during turn-off is given. >

On the reverse bias safe operating area of power bipolar transistors during inductive turn-off

The turnoff transient of power bipolar transistors, under inductive load, has been analyzed by a 2D numerical simulator in the region where impact ionization is present, with the purpose of investigating the factors which limit their reverse bias safe operating area (RBSOA). Results show that the geometry of the device elementary cell, as well as its doping concentration profile have a strong effect on the maximum voltage the device can withstand at high currents and on the stress the device undergoes during turnoff. The steady-state (or sustaining) voltage locus, calculated while the device is avalanching, allows to understand a basic reason for the decrease of maximum voltage at high currents, which is observed in the RBSOA of some devices, and allows to predict the shape of turnoff voltage waveforms, that are experimentally observed in recently developed devices. The use of power density maps allows to identify the basic differences among the different device structures, in terms of power concentration resulting from current crowding and impact ionization effects.

An improved detector scheme for nondestructive reverse bias safe operating area test systems

An enhanced second-breakdown detector for a nondestructive reverse bias safe operating area test system has been developed. The detector corrects the previously reported deficiencies in the original detector. In addition, the enhancements to the detector can detect a new second-breakdown waveform that had not previously been identified.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new approach to a nondestructive reverse bias safe operating area test system

An approach to a nondestructive reverse bias safe operating area (RBSOA) test system that greatly simplifies system construction while equaling the performance of previous systems has been developed. The approach is simpler because it utilizes a single solid state device as the primary component of the protection circuit instead of vacuum tubes. This is possible because the measurement technique utilized here effectively eliminates the turn-on delay of the protection circuit which includes the unacceptably long turn-on delay of the solid state device. The system also includes several new measurement modes that were not possible or available with previous systems. >

An 1800 V 300 A nondestructive tester for bipolar power transistors

A nondestructive reverse-bias safe operating area (RBSOA) tester using an ultra-fast shunt circuit is constructed and demonstrated up to an 1800 V 300 A level. An innovative MOSFET shunt circuit is the key to the high power capability of the tester. The tester is an upgraded version of the old tester (rated at 1000 V 120 A) reported by the authors in 1985. The basic operation of the tester is reviewed, the design and the fabrication of the new tester are described, and test results are provided.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design Considerations for Paralleling Bipolar Transistors

A simple design procedure for direct paralleling of bipolar junction transistors (BJT's) is proposed. It is based on the matching of transfer characteristics (Ic versus VCE) at a low collector voltage. The design procedure further addresses the base and collector circuit's layout requirements, optimal base-driven conditions, and thermal design requirements for reliable and efficient operation of BJT's in parallel. The influence of a snubber circuit is also discussed. The procedure is verified experimentally by performing dynamic and reversebias safe operating area (RBSOA) testings.

Nondestructive Characterization of RBSOA of High-Power Bipolar Transistors

Reverse-bias safe operating area (RBSOA) of high-power Darlington transistors is characterized using a 120 A/1000 V nondestructive reverse-bias second breakdown tester designed and fabricated at Virginia Polytechnic Institute and State University. Elaborate RBSOA characteristics are generated with different forward/reverse base drives and collector current levels. The effects of elevated case temperature and second-base drive on RBSOA of four-terminal Darlington devices are also discussed.