Resistive Random Access Memory Technology Research Articles

Ternary encoder and decoder designs in RRAM and CNTFET technologies

A possible way for the very large scale integration (VLSI) industry to keep up with the pace of high density, computational capability, and energy efficiency is to look into some technologies ahead of binary logic. In recent years, multiple-valued logic (MVL) has caught the notable attention of digital system designers. The carbon nanotube field effect transistor (CNTFET) has been exclusively used for the implementation of MVL circuits. Resistive random-access memory (RRAM) offers a very durable option for executing the MVL due to its capability of storing various resistance states in one cell. In this paper, a ternary 9:2 encoder and a ternary 2:9 decoder have been designed and simulated using the proposed RRAM-based ternary logic gates with standard 32nm CNTFETs. In comparison to other ternary circuits in the literature, the proposed CNTFET RRAM-based ternary logic circuits show less power consumption, delay, and power delay product (PDP). The power of the CNTFET RRAM-based proposed ternary inverter (TI), ternary NAND (TNAND), and ternary NOR (TNOR) is 32.78%, 51.48%, and 24.14% less than the lowest power of the other designs under consideration. The PVT variations and reliability of the proposed encoder and decoder circuits have also been studied.

Modeling the conduction mechanisms of intrinsic multi-level states in HfOx-based resistive random access memory

Multi-level cell storage technology based on resistive random access memory (RRAM) with multi-level state characteristics is more attractive in achieving low-cost ultra-high-density nonvolatile memory. Although a large number of literatures have reported the multi-level state characteristics of RRAM, so far there is no unified model that can well explain the intrinsic reasons for the existence of intermediate resistance state (IRS) and the switching mechanism between different resistance states. Multi-level state characteristics are observed by I–V characteristic measurements on RRAM with TiN/HfOx/barrier layer/TiN stacks fabricated using a commercialized 28 nm CMOS process. Compared to other published resistive switching models, the proposed model based on trap-assisted tunneling is more consistent with the measured. The model can reproduce the multi-level state characteristics based on the mechanism that interaction between defects and oxygen vacancies at the interface of HfOx and TiN electrode, resulting in the formation of multiple weak conductive filaments. Furthermore, the wide spread of high resistance state (HRS) and the switching between HRS and IRS are determined by the distance of tunneling gap. As HfOx-based RRAM will soon be commercialized, it is becoming very urgent to clarify the switching mechanisms of multi-level state characteristics and propose a universal model. Consequently, this work satisfied the current demand and significantly advanced the understanding and development of commercialized, cost-effective, high-density multi-bit HfOx-based RRAM technology.

Experimental Assessment of Multilevel RRAM-Based Vector-Matrix Multiplication Operations for In-Memory Computing

Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times $ </tex-math></inline-formula> 8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices’ nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems.

Comprehensive physics-based RRAM compact model including the effect of variability and multi-level random telegraph noise

Resistive Random Access Memory (RRAM) technologies are a promising candidate for the development of more energy efficient circuits, for computing, security, and storage applications. However, such devices show stochastic behaviours that not only originate from variations introduced during fabrication, but that are intrinsic to their operation. Specifically, cycle-to-cycle variations cause the programmed resistive state to be randomly distributed, while Random Telegraph Noise (RTN) introduces random current fluctuations over time. These phenomena can easily affect the reliability and performance of RRAM-based circuits. Therefore, designing such circuits requires accurate compact models. Although several RRAM compact models have been proposed in the literature, these are rarely implemented following the programming best-practice for improving the simulator convergence, and a compact model that is able to reproduce the device characteristic including thermal effects, RTN, and variability in multiple operating conditions using a single set of parameters is still missing. Also, only a few works in the literature describe the procedure to calibrate such compact models, and even fewer address the calibration of the variability on experimental data. In this work, we extend the UniMORE RRAM physics-based compact model by developing and validating two variability models, (i) a comprehensive variability model which can reproduce the effect of cycle-to-cycle variability in multiple operating conditions, and (ii) a simplified version that requires fewer calibration data and enables to reproduce cycle-to-cycle variations in specific operating conditions. The model is implemented following Verilog-A programming best-practices and validated on data from three RRAM technologies from the literature and experimentally on TiN/Ti/HfOx/TiN devices, and the relation between experimental data and the variability model parameters is described.

A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References

Resistive random access memory (RRAM)-based compute-in-memory (CIM) has shown great potential for accelerating deep neural network (DNN) inference. However, device characteristics, such as low-resistance values, susceptibility to drift, and single-level cells, may limit the capabilities of RRAM-based CIM. In addition, prior works generally used the off-chip write-verify scheme to tighten RRAM resistance distributions and used off-chip analog-to-digital converter (ADC) references for fine-tuning partial sum quantization. Although off-chip techniques are viable for testing purposes, they may be unsuitable for practical applications. In this work, we present an RRAM-CIM macro to accelerate DNN inference. The chip features: 1) multi-level cell (MLC) RRAM for improving compute performance and density; 2) sparsity-aware input control to leverage the high activation sparsity in DNN models; 3) on-chip write-verify to speed up initial weight programming and periodically refresh cells to compensate for resistance drift under stress; and 4) on-chip ADC reference generation that provides column-wise tunability and stability with varying temperatures to guarantee the CIFAR-10 accuracy of 85.8% at 120 °C. The design is fabricated in TSMC 40-nm process with embedded RRAM technology and achieves a macro-level peak performance of 97.8 GOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 44.5 TOPS/W for multiply-and-accumulate (MAC) operations on VGG-8 network with ternary weights.

An Efficient In-Memory Computing Architecture for Image Enhancement in AI Applications

Random Spray Retinex (RSR) is an effective image enhancement algorithm due to its effectiveness in improving image quality. However, the algorithm computing complexity and the required hardware resources and memory accesses hampered its deployment in many applications scenarios, for instance in IoT systems with limited hardware resources. With the rise of Artificial Intelligence (AI), the use of image enhancement has become essential to improve the performance for many emerging applications. In this paper, we propose the use of the RSR as a pre-processing filter before the task of semantic segmentation of low-quality urban road scenes. Using the publicly available Cityscapes dataset, we compare the performance of a pre-trained deep semantic segmentation network on dark noisy images and on RSR pre-processed images. Our findings confirm the effectiveness of RSR in improving segmentation accuracy. In addition, to address the computation complexity and suitability to edge devices, we propose a novel efficient implementation of the RSR using resistive random access memory (RRAM) technology. The architecture provides highly parallel analog in-memory computing (IMC) capabilities. A detailed, efficient and low latency implementation of the RSR using RRAM-CMOS technology is described. The design is verified using SPICE simulations with measured data from fabricated RRAM and 65nm CMOS technologies. The approach provided here represents an important step towards low-complexity and real-time hardware-friendly architecture and design for Retinex algorithms for edge devices.

A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection

Computing-in-memory (CIM) architectures have gained importance in achieving high-throughput energy-efficient artificial intelligence (AI) systems. Resistive RAM (RRAM) is a promising candidate for CIM architectures due to a multiply-and-accumulate (MAC)-friendly structure, high bit density, compatibility with a CMOS process, and nonvolatility. Notwithstanding the advancement of RRAM technology, the reliability of an RRAM array hinders the spread of RRAM applications such that a circuit-technology joint approach is necessary to attain reliable RRAM-based CIM architectures. This article presents a 64-kb hybrid CIM/digital RRAM macro supporting: 1) active-feedback-based voltage-sensing read (RD) to enable 1–8-b programmable vector-matrix multiplication under a low-resistance ratio of the high-resistance state to the low-resistance state in an RRAM array; 2) iterative write with verification to secure a tight resistance distribution; and 3) online RD-disturb detection in the background during CIM. The test chip fabricated in a 40-nm CMOS and RRAM process achieves a peak energy efficiency of 56.67 TOPS/W while demonstrating the eight-bitline hybrid CIM/digital MAC operation with 1–8-b inputs and weights and 20-b outputs without quantization.

Operando Direct Observation of Filament Formation in Resistive Switching Devices Enabled by a Topological Transformation Molecule.

Conductive filaments (CFs) play a critical role in the mechanism of resistive random-access memory (ReRAM) devices. However, in situ detection and visualization of the precise location of CFs are still key challenges. We demonstrate for the first time the use of a π-conjugated molecule which can transform between its twisted and planar states upon localized Joule heating generated within filament regions, thus reflecting the locations of the underlying CFs. Customized patterns of CFs were induced and observed by the π-conjugated molecule layer, which confirmed the hypothesis. Additionally, statistical studies on filaments distribution were conducted to study the effect of device sizes and bottom electrode heights, which serves to enhance the understanding of switching behavior and their variability at device level. Therefore, this approach has great potential in aiding the development of ReRAM technology.

Multi-Input Logic-in-Memory for Ultra-Low Power Non-Von Neumann Computing.

Logic-in-memory (LIM) circuits based on the material implication logic (IMPLY) and resistive random access memory (RRAM) technologies are a candidate solution for the development of ultra-low power non-von Neumann computing architectures. Such architectures could enable the energy-efficient implementation of hardware accelerators for novel edge computing paradigms such as binarized neural networks (BNNs) which rely on the execution of logic operations. In this work, we present the multi-input IMPLY operation implemented on a recently developed smart IMPLY architecture, SIMPLY, which improves the circuit reliability, reduces energy consumption, and breaks the strict design trade-offs of conventional architectures. We show that the generalization of the typical logic schemes used in LIM circuits to multi-input operations strongly reduces the execution time of complex functions needed for BNNs inference tasks (e.g., the 1-bit Full Addition, XNOR, Popcount). The performance of four different RRAM technologies is compared using circuit simulations leveraging a physics-based RRAM compact model. The proposed solution approaches the performance of its CMOS equivalent while bypassing the von Neumann bottleneck, which gives a huge improvement in bit error rate (by a factor of at least 108) and energy-delay product (projected up to a factor of 1010).

Reliability and Performance Analysis of Logic-in-Memory Based Binarized Neural Networks

Resistive Random access memory (RRAM) devices together with the material implication (IMPLY) logic are a promising computing scheme for realizing energy efficient reconfigurable computing hardware for edge computing applications. This approach has been recently shown to enable the in-memory implementation of Binarized Neural Networks. However, an accurate analysis of the performance achieved on a real classification task are still missing. In this work, we train and estimate the performance of an IMPLY-based implementation of a multilayer perceptron (MLP) BNN and highlight its main reliability challenges by using a physics-based RRAM compact model calibrated on three RRAM technologies from the literature. We then show how the smart IMPLY (SIMPLY) architecture solves the reliability issues of conventional IMPLY architectures and compare its performance with respect to conventional solutions considering different parallelization degree. The worst-case energy estimates for an inference task performed on the trained network, show that the SIMPLY implementation results in a >46 energy-delay-product (EDP) improvement with respect to a conventional low-power embedded system implementation.

0.5T0.5R—An Ultracompact RRAM Cell Uniquely Enabled by van der Waals Heterostructures

Conventional designs of the extensively studied resistive-random access-memory (RRAM) cell involve one transistor and one RRAM-“1T1R,” i.e., two separate devices thereby constraining its integration density. In this work, we overcome this longstanding limitation by experimentally demonstrating a novel memory architecture that combines the 1T and 1R into a single hybrid device by uniquely leveraging both lateral and vertical van der Waals (vdW) heterostructures. This ultracompact device, which can be considered as a “0.5T0.5R” memory cell, reduces the device count by half-the first of its kind in RRAM technology history, and simultaneously allows higher lateral as well as vertical (3-D) integration density w.r.t. the conventional 1T1R architecture. The unique “smart” device that can retain information after power is turned off is structurally designed by utilizing a shared graphene edge-contact and resistively switchable hexagonal boron nitride ( h-BN) insulator. Aided by design optimization, record performance(10 ns switching-speed), energy- (~0.07 pJ/bit), and area-efficiency (smallest footprint among all reported vdW-material-based RRAM memory units), as well as great retention (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> s) and endurance (>1000), benchmarked against current vdW-material-based RRAM devices, have been achieved by this 0.5T0.5R memory cell. Moreover, the RRAM's fine tunability with ultrashort pulsewidth, pulse amplitude, and gate voltage, enables synaptic plasticity and makes it an integrated three-terminal RRAM with considerable potential for neuromorphic and in-memory computing applications.

A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells

In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.

A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices

The development of small, energy-efficient artificial intelligence edge devices is limited in conventional computing architectures by the need to transfer data between the processor and memory. Non-volatile compute-in-memory (nvCIM) architectures have the potential to overcome such issues, but the development of high-bit-precision configurations required for dot-product operations remains challenging. In particular, input–output parallelism and cell-area limitations, as well as signal margin degradation, computing latency in multibit analogue readout operations and manufacturing challenges, still need to be addressed. Here we report a 2 Mb nvCIM macro (which combines memory cells and related peripheral circuitry) that is based on single-level cell resistive random-access memory devices and is fabricated in a 22 nm complementary metal–oxide–semiconductor foundry process. Compared with previous nvCIM schemes, our macro can perform multibit dot-product operations with increased input–output parallelism, reduced cell-array area, improved accuracy, and reduced computing latency and energy consumption. The macro can, in particular, achieve latencies between 9.2 and 18.3 ns, and energy efficiencies between 146.21 and 36.61 tera-operations per second per watt, for binary and multibit input–weight–output configurations, respectively. Commercial complementary metal–oxide–semiconductor and resistive random-access memory technologies can be used to create multibit compute-in-memory circuits capable of fast and energy-efficient inference for use in small artificial intelligence edge devices.

Analogue pattern recognition with stochastic switching binary CMOS-integrated memristive devices

Biological neural networks outperform current computer technology in terms of power consumption and computing speed while performing associative tasks, such as pattern recognition. The analogue and massive parallel in-memory computing in biology differs strongly from conventional transistor electronics that rely on the von Neumann architecture. Therefore, novel bio-inspired computing architectures have been attracting a lot of attention in the field of neuromorphic computing. Here, memristive devices, which serve as non-volatile resistive memory, are employed to emulate the plastic behaviour of biological synapses. In particular, CMOS integrated resistive random access memory (RRAM) devices are promising candidates to extend conventional CMOS technology to neuromorphic systems. However, dealing with the inherent stochasticity of resistive switching can be challenging for network performance. In this work, the probabilistic switching is exploited to emulate stochastic plasticity with fully CMOS integrated binary RRAM devices. Two different RRAM technologies with different device variabilities are investigated in detail, and their potential applications in stochastic artificial neural networks (StochANNs) capable of solving MNIST pattern recognition tasks is examined. A mixed-signal implementation with hardware synapses and software neurons combined with numerical simulations shows that the proposed concept of stochastic computing is able to process analogue data with binary memory cells.

Non-volatile SRAM memory cells based on ReRAM technology

Static Random-Access Memories (SRAMs) are very common in today’s chip industry due to their speed and power consumption but are classified as volatile memories. Non-volatile SRAMs (nvSRAMs) combine SRAM features with non-volatility. This combination has the advantage to retain data after power off or in the case of power failure, enabling energy-efficient and reliable systems under frequent power-off conditions. In this work, several nvSRAMs architectures based on Oxide Random-Access Memory (OxRAM) technology are presented and compared. OxRAMs are non-volatile memories considered as a subset of Resistive RAM (ReRAM) technology.

Challenges and Applications of Emerging Nonvolatile Memory Devices

Emerging nonvolatile memory (eNVM) devices are pushing the limits of emerging applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Among several alternatives, phase change memory, spin-transfer torque random access memory, and resistive random-access memory (RRAM) are major emerging technologies. This review explains all varieties of prototype and eNVM devices, their challenges, and their applications. A performance comparison shows that it is difficult to achieve a “universal memory” which can fulfill all requirements. Compared to other emerging alternative devices, RRAM technology is showing promise with its highly scalable, cost-effective, simple two-terminal structure, low-voltage and ultra-low-power operation capabilities, high-speed switching with high-endurance, long retention, and the possibility of three-dimensional integration for high-density applications. More precisely, this review explains the journey and device engineering of RRAM with various architectures. The challenges in different prototype and eNVM devices is disused with the conventional and novel application areas. Compare to other technologies, RRAM is the most promising approach which can be applicable as high-density memory, storage class memory, neuromorphic computing, and also in hardware security. In the post-CMOS era, a more efficient, intelligent, and secure computing system is possible to design with the help of eNVM devices.

Exploring the Impact of Random Telegraph Noise-Induced Accuracy Loss on Resistive RAM-Based Deep Neural Network

For resistive RAM (RRAM)-based deep neural network (DNN), random telegraph noise (RTN) causes accuracy loss during inference. In this article, we systematically investigated the impact of RTN on the complex DNNs with different data sets. By using eight mainstream DNNs and four data sets, we explored the origin that caused the RTN-induced accuracy loss. Based on the understanding, for the first time, we proposed a new method to estimate the accuracy loss. The method was verified with other ten DNN/data set combinations that were not used for establishing the method. Finally, we discussed its potential adoption for the cooptimization of the DNN architecture and the RRAM technology, paving ways to RTN-induced accuracy loss mitigation for future neuromorphic hardware systems.

ReRAM: History, Status, and Future

This article reviews the resistive random-access memory (ReRAM) technology initialization back in the 1960s and its heavily focused research and development from the early 2000s. This review goes through various oxygen/oxygen vacancy and metal-ion-based ReRAM devices and their operation mechanisms. This review also benchmarks the performance of various oxygen/oxygen vacancy and metal-ion-based ReRAM devices with general trend drawn. Being a semiconductor memory and storage technology, the commercialization attempts for both stand-alone mass storage/storage-class memory and embedded nonvolatile memory are also reviewed. Looking toward the coming era, the potential of using ReRAM technology to improve machine learning efficiency is discussed.

Incorporating Variability of Resistive RAM in Circuit Simulations Using the Stanford–PKU Model

Intrinsic variability observed in resistive-switching devices (cycle-to-cycle and device-to-device) is widely recognised as a major hurdle for widespread adoption of Resistive RAM technology. While physics-based models have been developed to accurately reproduce the resistive-switching behaviour, reproducing the observed variability behavior of a specific RRAM has not been studied. Without a properly fitted variability in the model, the simulation error introduced at the device-level propagates through circuit-level to system-level simulations in an unpredictable manner. In this work, we propose an algorithm to fit a certain amount of variability to an existing physics-based analytical model (Stanford-PKU model). The extent of variability exhibited by the device is fitted to the model in a manner agnostic to the cause of variability. Further, the model is modified to better reproduce the variations observed in a device. The model, fitted with variability can well reproduce cycle-to-cycle, as well as device-to-device variations. The significance of integrating variability into RRAM models is underscored using a sensing example.

A Study on the Interfacial Structure Design of Self‐Compliance Ni/HfOx/Ni Bipolar Selectors and Trap‐to‐Trap Tunneling Mechanism Caused by Redox Reaction

Selectors are considered some of the most significant devices applied to the integration of resistive random access memory (RRAM). Self‐compliance selectors promote the stability of one selector and one resistor (1S1R) cell to reduce additional compliance current circuits without compromising RRAM switching performance. Herein, a Ni/HfOx/Ni bipolar selector with special cluster microstructures is fabricated via a facial magnetron sputtering technology, which has self‐compliance (±12 μA) performance and ultrahigh voltage endurance (±10 V). To investigate the mechanism, theoretical models for the self‐compliance selectors are proposed. The results demonstrate that traps and special interfaces are formed through redox reactions. Resistive switching properties are caused by the trap‐to‐trap tunneling structure of the HfOx–NiOy layers. At the interfaces of HfOx–NiOy oxide layers, the tunneling current reaches a saturation state, leading to the self‐compliance phenomenon, which provides a theoretical and research foundation for the development of RRAM technology.