Abstract
Conventional designs of the extensively studied resistive-random access-memory (RRAM) cell involve one transistor and one RRAM-“1T1R,” i.e., two separate devices thereby constraining its integration density. In this work, we overcome this longstanding limitation by experimentally demonstrating a novel memory architecture that combines the 1T and 1R into a single hybrid device by uniquely leveraging both lateral and vertical van der Waals (vdW) heterostructures. This ultracompact device, which can be considered as a “0.5T0.5R” memory cell, reduces the device count by half-the first of its kind in RRAM technology history, and simultaneously allows higher lateral as well as vertical (3-D) integration density w.r.t. the conventional 1T1R architecture. The unique “smart” device that can retain information after power is turned off is structurally designed by utilizing a shared graphene edge-contact and resistively switchable hexagonal boron nitride ( h-BN) insulator. Aided by design optimization, record performance(10 ns switching-speed), energy- (~0.07 pJ/bit), and area-efficiency (smallest footprint among all reported vdW-material-based RRAM memory units), as well as great retention (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> s) and endurance (>1000), benchmarked against current vdW-material-based RRAM devices, have been achieved by this 0.5T0.5R memory cell. Moreover, the RRAM's fine tunability with ultrashort pulsewidth, pulse amplitude, and gate voltage, enables synaptic plasticity and makes it an integrated three-terminal RRAM with considerable potential for neuromorphic and in-memory computing applications.
Highlights
T RADITIONAL von Neumann architecture with physically separated processing and memory units is undergoing a significant paradigm-shift since transistor-based serial logic computing technology can no longer provide historical energy-efficiency and noticeable performance benefits for the recent flourishing growth in highly data-driven artificial intelligence applications
Monolayer graphene with an atomically thin body, high conductivity, and strong sp2 bonding serving as source line (SL) electrode can mitigate the oxidation at the interface between the electrode and the switching layer
In order to fully exploit the advantages of resistive-random access-memory (RRAM) in large-scale memory array [Fig. 1(b)], one of the practical solutions is to connect a transistor in series with each RRAM, i.e., in the form of 1T1R, in order to suppress the sneak current from the inactive memory units [18] [Fig. 1(c) and (d)], thereby improving the reliability and sta
Summary
T RADITIONAL von Neumann architecture with physically separated processing and memory units is undergoing a significant paradigm-shift since transistor-based serial logic computing technology can no longer provide historical energy-efficiency and noticeable performance benefits for the recent flourishing growth in highly data-driven artificial intelligence applications. RRAM is considered as one of the most promising next-generation memory devices due to its nonvolatility, high switching-speed, low switching-energy, and small footprint [5]–[8], especially as the necessity of data-centric applications is exponentially growing in this twenty-first century These merits make it a strong contender for conventional digital memory such as cache memory (SRAM) and dynamic RAM (DRAM), etc., and for analog memristors in the emerging neuromorphic computing domain [9]–[12]. Due to the relatively larger formation energy of boron vacancy [14]–[16] and dangling-bond-free surface [17], the oxygen-less hexagonalboron nitride (h-BN) as switching layer provides superior chemical stability, alleviating any oxidation reaction to metallic filaments and preventing redundant creation of undesirable vacancies.
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