3D Vertical RRAM Array and Device Co-design with Physics-based Spice Model

Abstract

This paper demonstrates the co-design of three-dimension (3D) Vertical Resistive Random Access Memory (RRAM) and the RRAM device. It presents a design consideration of 3D Vertical RRAM array in terms of array performance from the device point of view. A physics-based RRAM Spice model is used to evaluate the performance of 3D RRAM array, including write access voltage, read margin, energy consumption and switching speed. The effects of device parameters, device parasitic capacitance, device variation and the 3D array size are discussed for design consideration. The simulation results show that with carefully choosing the RRAM device material and structure, a fast-switching, low energy consumption 3D RRAM array can be realized.