Impact of Etch Process on Hafnium Dioxide Based Nanoscale RRAM Devices

Abstract

Resistive Random Access Memory (RRAM) is a new class of electronic device whose resistance level can be modulated by feeding a current through the device. The resistance level (memory state) of RRAM devices is non-volatile, making them a viable replacement for flash memory. In addition, this characteristic can be utilized for various circuit level designs including neuro-inspired hardware. For instance, RRAM devices can emulate the relative strength of neural synapses by encoding variable resistance states. In this contribution we integrated a RRAM devices with CMOS fabricated on a 300mm wafer platform. The IBM 65nm 10LPe process technology was used as a base for this customized integration effort, with modifications to accommodate the RRAM devices between metal 1 (M1) and metal 2 (M2). By changing the M1 interconnect to tungsten it is possible to utilize front-end-of-the-line (FEOL) tools for the hafnium dioxide atomic layer deposition. Above the custom tungsten M1 layer, a dual tungsten/copper via structure was developed to accommodate RRAM device fabrication. The hafnium dioxide RRAM switching layer was capped with a titanium oxygen getter layer and an inert titanium nitride electrode. The capping layers were etched with reactive ion etch (RIE) whereas two approaches were tested for the hafnium dioxide removal: 1) a wet etch with diluted hydrofluoric acid (dHF) and 2) a BCl3 based reactive ion etch (RIE) process. The test platform for the vertically-integrated RRAM devices included: 1) 12x12 crossbar arrays with 100x100 nm2 size devices 2) single RRAM (1R) devices with sizes ranging from 100x100 nm2 to 10x10 µm2 and 3) 1 transistor 1 RRAM (1T1R) structures with 100x100 nm2 size devices. The impact on the RRAM devices for both etch processes was investigated with respect to the physical structure, the electrical characteristics and the yield. The electrical characteristics include simple I-V DC sweeps, pulse-based endurance measurements, retention measurements as well as pulse dependent behavior showing an incremental reset. The functional principle these RRAM devices is consistent with a valence change mechanism (VCM), which is filament-based, and therefore area independent. RRAM devices fabricated using the dHF wet etch with layer thicknesses of 5.8 nm of hafnium dioxide and 6 nm of titanium exhibited endurance values exceeding 108 cycles with an average on/off resistance ratio of 5 and set/reset voltages below 1/-1.5 V. The dHF etch negatively impacted the physical device structure of the RRAM devices, which was reflected by the resulting electrical performance. By moving to a dry etching (RIE) process, an improvement in yield, reliability, endurance and retention is expected. In particular, yield is expected to increase due to reduced undercut of the titanium oxygen getter layer, which is characteristic of the dHF etch. In summary, this work shows the importance of etch performance and selectivity for optimization of RRAM device performance.