Resistive Random Access Memory Array Research Articles

Electric conductivity of remotely heated Cu nanofilaments in Cu/TaOx/Pt ReRAM cells

A memory cell, initially set to a conductive state, of a resistive resistive random access memory array is heated remotely and controllably by a neighboring heat source cell, both cells having either a common active or an inert electrode. Upon switching off the heating of the heat source cell, the conductivity of the filament of the investigated cell is characterized by sufficiently small voltages to make sure that the filament does not suffer any structural reconstruction such as removal, addition, or permanent displacement of Cu atoms. One observes that immediately after the heating of the neighboring heat source device is switched off, the cell, initially set to an on state and characterized by a low resistance Ron, is found to be reset by remote heating to an off state, characterized by R off ≫ R on. In some instances, after a cooling off time of approximately 2 min or more, one observes the cell's spontaneous recovery from the Roff state to the original on state or very close to the initial Ron value. The process of the spontaneous recovery of the electric conductivity of the filament is interpreted as an attenuation of Cu atom vibrations in the filament with the attendant increase of electron tunneling effects for which the variation of the average tunneling distance between the vibrating Cu atoms is roughly proportional to the square root of the absolute temperature. At high temperatures, the average tunneling distance increases, leading to a sharp decrease of the tunneling probability and, consequently, to a sharp increase in transient resistance.

Mixed-Signal Neuromorphic Computing Circuits Using Hybrid CMOS-RRAM Integration

Recent integration of Resistive Random Access Memory (RRAM) with standard CMOS has spurred exploration of high-density and low-power in-memory computing. RRAM arrays are being intensely investigated for analog-domain Vector Matrix Multiplication (VMM) and Neuromorphic Computing. However, to exploit the advantages of RRAM over other forms of nonvolatile memories, mixed-signal circuit designers need to accommodate their device nonidealities, and design circuits to translate high-level deep neural network algorithms to mixed-signal hardware. This brief reviews the field of neuromorphic computing using hybrid CMOS-RRAM circuits, associated circuit design challenges, and potential approaches for their mitigation, followed by benchmarking of recent demonstrations.

A Seamless, Reconfigurable, and Highly Parallel In-Memory Stochastic Computing Approach With Resistive Random Access Memory Array

A seamless, reconfigurable, and highly parallel in-memory stochastic computing (SC) approach is proposed and experimentally demonstrated in resistive random access memory (RRAM) array. By utilizing the probabilistic switching behavior of RRAM and parallel writing, stochastic bit streams (SBS) are generated in parallel. By employing in-memory stateful logic, parallel stochastic logic is directly performed within the same memory array. This in-memory SC approach has three merits: 1) true stochastic number generator (SNG) can be obtained with low cost, 2) the signal conversion overhead between SNG and stochastic logic is eliminated, 3) it is highly parallel and the stochastic logic is reconfigurable. This work provides an efficient and low-cost alternative approach to achieve SC.

Two-step write–verify scheme and impact of the read noise in multilevel RRAM-based inference engine

Accurate cell conductance tuning is critical to realizing multilevel resistive random access memory (RRAM)-based compute-in-memory inference engines. To tighten the distribution of the cells of each state, we developed a two-step write–verify scheme within a limited number of iterations, which was tested on a test vehicle based on HfO2 RRAM array to realize 2 bits per cell. The conductance of the cells is gathered in the targeted range within 10 loops of set and reset processes for each step. Moreover, the read noise of the RRAM cells is statistically measured and its impact on the upper bound of analog-to-digital converter (ADC) resolution is predicted. The result shows that the intermediate state cells under relatively high read voltage (e.g. 0.2 V) are vulnerable to the read noise. Fortunately, the aggregated read noise along the column will not disturb the output of a 5 bit ADC that is required for a 128 × 128 array with 2 bits per cell.

Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays

Logic-in-memory (LiM) circuits based on resistive random access memory (RRAM) devices and the material implication logic are promising candidates for the development of low-power computing devices that could fulfill the growing demand of distributed computing systems. However, these circuits are affected by many reliability challenges that arise from device nonidealities (e.g., variability) and the characteristics of the employed circuit architecture. Thus, an accurate investigation of the variability at the array level is needed to evaluate the reliability and performance of such circuit architectures. In this work, we explore the reliability and performance of smart IMPLY (SIMPLY) (i.e., a recently proposed LiM architecture with improved reliability and performance) on two 4-kb RRAM arrays based on different resistive switching oxides integrated in the back end of line (BEOL) of the 0.25-μm BiCMOS process. We analyze the tradeoff between reliability and energy consumption of SIMPLY architecture by exploiting the results of an extensive array-level variability characterization of the two technologies. Finally, we study the worst case performance of a full adder implemented with the SIMPLY architecture and benchmark it on the analogous CMOS implementation.

Analytical modelling of tantalum/titanium oxide‐based multi‐layer selector to eliminate sneak path current in RRAM arrays

One selector-one resistor (1S-1R) configuration is desirable to use in conductive bridge resistive random-access memory (CBRAM) and resistive random-access memory (RRAM) crossbar arrays (CBAs) to reduce sneak path current. In this study, an analytical model of Ta2O5/TaOx/TiO2 selector device is developed and is integrated with RRAM model to demonstrate the acquired features of 1S-1R to reduce the sneak path current. The proposed selector model is developed by considering the electric field-driven tunnelling mechanisms co-exist in thin multi-layer devices such as direct and Fowler-Nordheim tunnelling. The simulated characteristics of proposed model shows high non-linearity (∼1600), high selectivity (∼104), high current density (∼107 A/cm2) and low off current (∼46 nA). Further, the proposed model is simulated with different top electrode metals and dielectric materials to demonstrate the formation of optimal stack for the desired application. Then, the proposed selector model (1S) is integrated with RRAM model (1R) and the compatibility of the devices is verified. Moreover, from the presented 1S-1R model, various parameters for the establishment of CBA such as read/write voltages for selected/unselected trails are predicted and substantial conditions for sneak path current reduction such as non-linearity, Roff/Ron ratio and off-current (10 nA) are also evaluated.

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives.

Evaluating Neural Network-Inspired Analog-to-Digital Conversion With Low-Precision RRAM

Recent work has demonstrated great potentials of neural network-inspired analog-to-digital converters (NNADCs) in many emerging applications. These NNADCs often rely on resistive random-access memory (RRAM) devices to realize basic NN operations, and usually need high-precision RRAM (6–12 b) to achieve moderate quantization resolutions (4–8 b). Such an optimistic assumption of RRAM precision, however, is not well supported by practical RRAM arrays in the large-scale production process. In this article, we evaluate two new designs of NNADC with low-precision RRAM devices. They take advantage of traditional two-stage/pipelined hardware architecture and a custom deep-learning-based building block design methodology. Results obtained from SPICE simulations demonstrate a robust design of an 8-b subranging NNADC using 4-b RRAM devices, as well as a 14-b pipelined NNADC using 3-b RRAM devices. The evaluations on the two NNADCs suggest that pipelined architecture is better to achieve higher-resolution using lower precision RRAM. We also perform design space exploration on the building blocks of NNADCs to achieve a balanced performance tradeoff. Comprehensive comparisons reveal improved power, speed performance, and competitive figure of merits (FoMs) of the pipelined NNADC, compared with state-of-the-art NNADCs and traditional ADCs. In addition, the proposed pipelined NNADC can support reconfigurable high-resolution nonlinear quantization with high conversion speed and low conversion energy, enabling intelligent analog-to-information interfaces for near-sensor processing.

AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3-D Architecture

The growing popularity of convolutional neural networks (CNNs) along with their complexity has led to the search for efficient computational platforms suitable for them. Resistive random-access memory (ReRAM)-based architectures offer a promising alternative to commonly used GPU-based platforms for training CNNs. However, due to their low-precision storage capability, these architectures cannot support all types of CNN layers and suffer from accuracy loss of the learned model. In addition, ReRAM behavior varies with temperature. High temperature reduces noise margin and introduces additional noise. This makes training of CNNs challenging as outputs can be misinterpreted at higher operating temperatures leading to accuracy loss. In this work, we propose an M3D-enabled heterogeneous architecture: AccuReD, that combines ReRAM arrays with GPU cores, to address these challenges and achieve high accuracy CNN training. AccuReD supports all types of CNN layers and achieve near-GPU accuracy even with low-precision and nonideal behavior of ReRAMs. In addition, to reduce temperature, we present a performance-thermal-aware mapping policy that maps CNN layers to the computing elements of AccuReD. Experimental evaluation indicates that AccuReD does not lose accuracy while accelerating CNN training by 12× on an average compared to conventional GPU-only platforms.

A Fully Integrated Reprogrammable CMOS-RRAM Compute-in-Memory Coprocessor for Neuromorphic Applications

Analog compute-in-memory with resistive random access memory (RRAM) devices promises to overcome the data movement bottleneck in data-intensive artificial intelligence (AI) and machine learning. RRAM crossbar arrays improve the efficiency of vector-matrix multiplications (VMMs), which is a vital operation in these applications. The prototype IC is the first complete, fully integrated analog-RRAM CMOS coprocessor. This article focuses on the digital and analog circuitry that supports efficient and flexible RRAM-based computation. A passive $54\times108$ RRAM crossbar array performs VMM in the analog domain. Specialized mixed-signal circuits stimulate and read the outputs of the RRAM crossbar. The single-chip CMOS prototype includes a reduced instruction set computer (RISC) processor interfaced to a memory-mapped mixed-signal core. In the mixed-signal core, ADCs and DACs interface with the passive RRAM crossbar. The RISC processor controls the mixed-signal circuits and the algorithm data path. The system is fully programmable and supports forward and backward propagation. As proof of concept, a fully integrated 0.18- $\mu \text{m}$ CMOS prototype with a postprocessed RRAM array demonstrates several key functions of machine learning, including online learning. The mixed-signal core consumes 64 mW at an operating frequency of 148 MHz. The total system power consumption considering the mixed-signal circuitry, the digital processor, and the passive RRAM array is 307 mW. The maximum theoretical throughput is 2.6 GOPS at an efficiency of 8.5 GOPS/W.

Investigation of Read Disturb and Bipolar Read Scheme on Multilevel RRAM-Based Deep Learning Inference Engine

The multilevel resistive random access memory (RRAM)-based synaptic array can enable parallel computations of vector–matrix multiplication for machine learning inference acceleration; however, any conductance drift of the cell may induce an inference accuracy drop because the analog current is summed up along the column. In this article, the read disturb-induced conductance drift characteristic is statistically measured on a test vehicle based on 2-bit HfO2 RRAM array. The drift behavior of four states is empirically modeled by a vertical and lateral filament growth mechanism. Furthermore, a bipolar read scheme is proposed and tested to enhance the resilience against the read disturb. The modeled read disturb and proposed compensation scheme are incorporated into a VGG-like convolutional neural network for CIFAR-10 data set inference.

Programming Pulse Width Assessment for Reliable and Low-Energy Endurance Performance in Al:HfO2-Based RRAM Arrays

A crucial step in order to achieve fast and low-energy switching operations in resistive random access memory (RRAM) memories is the reduction of the programming pulse width. In this study, the incremental step pulse with verify algorithm (ISPVA) was implemented by using different pulse widths between 10 μ s and 50 ns and assessed on Al-doped HfO 2 4 kbit RRAM memory arrays. The switching stability was assessed by means of an endurance test of 1k cycles. Both conductive levels and voltages needed for switching showed a remarkable good behavior along 1k reset/set cycles regardless the programming pulse width implemented. Nevertheless, the distributions of voltages as well as the amount of energy required to carry out the switching operations were definitely affected by the value of the pulse width. In addition, the data retention was evaluated after the endurance analysis by annealing the RRAM devices at 150 °C along 100 h. Just an almost negligible increase on the rate of degradation of about 1 μ A at the end of the 100 h of annealing was reported between those samples programmed by employing a pulse width of 10 μ s and those employing 50 ns. Finally, an endurance performance of 200k cycles without any degradation was achieved on 128 RRAM devices by using programming pulses of 100 ns width.

Accurate Inference With Inaccurate RRAM Devices: A Joint Algorithm-Design Solution

Resistive random access memory (RRAM) is a promising technology for energy-efficient neuromorphic accelerators. However, when a pretrained deep neural network (DNN) model is programmed to an RRAM array for inference, the model suffers from accuracy degradation due to RRAM nonidealities, such as device variations, quantization error, and stuck-at-faults. Previous solutions involving multiple read–verify–write (R-V-W) to the RRAM cells require cell-by-cell compensation and, thus, an excessive amount of processing time. In this article, we propose a joint algorithm-design solution to mitigate the accuracy degradation. We first leverage knowledge distillation (KD), where the model is trained with the RRAM nonidealities to increase the robustness of the model under device variations. Furthermore, we propose random sparse adaptation (RSA), which integrates a small on-chip memory with the main RRAM array for postmapping adaptation. Only the on-chip memory is updated to recover the inference accuracy. The joint algorithm-design solution achieves the state-of-the-art accuracy of 99.41% for MNIST (LeNet-5) and 91.86% for CIFAR-10 (VGG-16) with up to 5% parameters as overhead while providing a 15– $150\times $ speedup compared with R-V-W.

A Parallel Multibit Programing Scheme With High Precision for RRAM-Based Neuromorphic Systems

Resistive random access memory (RRAM) has been extensively studied as a promising candidate for neuromorphic computing. So far, high-precision multibit programing of RRAM for neuromorphic systems is done cell-by-cell, which can be very time-consuming. This brief demonstrates a row-by-row parallel program-verify scheme on a fabricated 160-Kb RRAM array using the incremental gate voltage programing (IGVP) method. Statistical analysis indicates that the optimal conductance tuning step size can accelerate the programing process and improve the success rate. Also, for the first time, the fundamental relations between programing success rate, critical path, and parallel efficiency for parallel program-verify methodology on the RRAM array are systematically studied. Moreover, a software-comparable recognition accuracy with only <0.3% accuracy loss is experimentally achieved for MNIST data set classification utilizing the proposed parallel program-verify scheme.

A Compact Model of Analog RRAM With Device and Array Nonideal Effects for Neuromorphic Systems

The parallelism and analog computing features of neuromorphic systems bring great challenges in developing a compact model of analog resistive random access memory (RRAM). In this article, we develop a physics-based compact model for analog RRAM devices and crossbar array. Nonideal effects of analog RRAM device, such as variability, ${I}$ – ${V}$ nonlinearity, programming nonlinearity and asymmetry, and tuning voltage sensitivity, are modeled and verified with the statistical data measured from RRAM array. Modeling of parallel-vector-matrix-multiplication and weight update process on RRAM crossbars with interconnect resistance enables fast and accurate estimation of the training accuracy. Benchmarks of neural networks under different hardware conditions validate the functionality of the proposed model. This model can provide valuable design guidelines for a practical neuromorphic system with high performance and computing accuracy.

RED: A ReRAM-Based Efficient Accelerator for Deconvolutional Computation

Deconvolution is a key component in contemporary neural networks, especially, generative adversarial networks (GANs) and fully convolutional networks (FCNs). Due to extra operations of deconvolution compared to convolution, considerable degradation of performance, as well as energy efficiency is incurred when implementing deconvolution on the existing resistive random access memory (ReRAM)-based processing-in-memory (PIM) accelerators. In this article, we propose an ReRAM-based accelerator design, RED, for providing high-performance and low-energy deconvolution. We analyze the deconvolution execution on the existing ReRAM-based PIMs and utilize its interior computation pattern for design optimization. RED includes two major contributions: 1) pixel-wise mapping scheme and 2) zero-skipping data flow. Pixel-wise mapping scheme removes the zero insertion and performs convolutions over several ReRAM arrays and thus enables parallel computations with nonzero inputs. Zero-skipping data flow, assisted with customized input buffers design, enhances the computation parallelism and input data reuse. In evaluation, we compare RED against the existing ReRAM-based PIMs and CMOS-based counterpart with a variety of GAN and FCN models, each of which contains multiple deconvolution layers. The experimental results show that RED achieves a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.0\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$56.16\times $ </tex-math></inline-formula> speedup and a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.05\times $ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$18.17\times $ </tex-math></inline-formula> energy efficiency improvement over previous related accelerator designs.

A Self‐Terminated Operation Scheme for High‐Parallel and Energy‐Efficient Forming of RRAM Array

AbstractBy introducing a capacitor in series (CST), a self‐terminated (ST) operation scheme is proposed to achieve high‐parallel forming of resistive random access memory (RRAM) array with reduced time and energy consumption. Once the RRAM cell is switched to the low‐resistance state, the current is automatically cut off by the capacitor, which can significantly improve the parallelism and energy efficiency. The wire capacitance of interconnect (Cwire) can be utilized as CST, which means there is no addition circuit or process expense for the proposed ST scheme. After successful experimental verification of the proposed ST operation scheme in 1 kb RRAM array, the performance of 1 Gb RRAM memory is evaluated, which shows × 103 improvement in forming time (from 0.6 h to 0.84 s) and × 104 improvement in energy consumption. Moreover, by experimentally leveraging the operation scheme for array forming, the operation current is reduced in subsequent switching process without deteriorating the device reliability, which demonstrates the feasibility of the proposed ST operation scheme and its potential in low power applications.

The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates

The synthesis method of logic circuits based on the RRAM (Resistive Random Access Memory) devices is of great concern in recent years. Inspired by the CMOS-like RRAM based logic gates, this work proposes a NMOS-like RRAM gate family. The advantages of the proposed NMOS-like RRAM gates include: (1) all the gate circuits are array-implementable; (2) the gate family is logic complete; (3) the NOR, AND and NOT gates only consume single cycle respectively in the computation phase; (4) the gate circuits save half number of RRAM devices compared with the CMOS-like RRAM based counterparts. Furthermore, the synthesis method of logic circuits based on the NMOS-like RRAM gates is proposed and discussed. The single-cycle NMOS-like RRAM gates are utilized in priority under the constraints of the logic block. The features of the proposed synthesis method are: (1) it generates the high-performance logic circuits because the NMOS-like RRAM based gates work in parallel; (2) the logic block based on the proposed NMOS-like gates can be realized in the RRAM array; (3) the large-scale logic functions can be implemented by cascading the logic blocks. The in-array full-adder circuit generated by the proposed synthesis method only consumes three cycles in minimum, which outperforms the previous RRAM based counterpart. The synthesis results on the benchmark circuits show that the proposed synthesis method is able to generate the high-performance circuit in RRAM arrays for arbitrary logic functions.

2-Bit-Per-Cell RRAM-Based In-Memory Computing for Area-/Energy-Efficient Deep Learning

In-memory computing (IMC) has emerged as a promising technique for enhancing energy efficiency of deep neural networks (DNNs). While embedded nonvolatile memory, such as resistive RAM (RRAM) is a good alternative to SRAM/DRAM for IMC owing to high density, low leakage, and nondestructive read, most prior works have not demonstrated using multilevel RRAM devices for array-level IMC operations. In this letter, we present an IMC prototype with 2-bit-per-cell RRAM devices for area-/energy-efficient DNN inference. Optimizations on four-level conductance distribution and peripheral circuits with input-splitting scheme have been performed, enabling high DNN accuracy and low area/energy consumption. The prototype chip that monolithically integrated 90-nm CMOS and 2-bit-per- cell RRAM array achieves 87% (83%) CIFAR-10 accuracy and 25 (51) TOPS/W energy efficiency at 1.2 V (0.9 V) supply. At 1.2 V, a stable accuracy of ~87% is maintained throughout 108 h.

Influence of specific forming algorithms on the device-to-device variability of memristive Al-doped HfO2 arrays

In this work, the influence of specific switching algorithms on device-to-device (D2D) variability of the forming process, in an integrated Al-doped HfO2 1T-1R 4 kbit resistive random access memory array, is investigated. The resistive devices are programed by using two different algorithms: the incremental step pulse and verify algorithm (ISPVA) at different temperatures and the constant amplitude pulse and verify algorithm (CAPVA) at different voltage amplitudes. The stabilized forming currents of both algorithms are compared in terms of their distributions, yields, and dispersions. The D2D distributions of the forming voltages of ISPVA and the forming times of CAPVA are fitted by Weibull distributions. The obtained Weibull parameters provide a link with the statistics governing the process. Finally, the authors discuss the importance of the ISPVA, CAPVA, temperature, and voltage amplitudes to improve the reliability of the forming process.