Programming Pulse Width Assessment for Reliable and Low-Energy Endurance Performance in Al:HfO2-Based RRAM Arrays

Eduardo Pérez,Helena Castán,Salvador Dueñas,Héctor García,Óscar González Ossorio,Christian Wenger

doi:10.3390/electronics9050864

Abstract

A crucial step in order to achieve fast and low-energy switching operations in resistive random access memory (RRAM) memories is the reduction of the programming pulse width. In this study, the incremental step pulse with verify algorithm (ISPVA) was implemented by using different pulse widths between 10 μ s and 50 ns and assessed on Al-doped HfO 2 4 kbit RRAM memory arrays. The switching stability was assessed by means of an endurance test of 1k cycles. Both conductive levels and voltages needed for switching showed a remarkable good behavior along 1k reset/set cycles regardless the programming pulse width implemented. Nevertheless, the distributions of voltages as well as the amount of energy required to carry out the switching operations were definitely affected by the value of the pulse width. In addition, the data retention was evaluated after the endurance analysis by annealing the RRAM devices at 150 °C along 100 h. Just an almost negligible increase on the rate of degradation of about 1 μ A at the end of the 100 h of annealing was reported between those samples programmed by employing a pulse width of 10 μ s and those employing 50 ns. Finally, an endurance performance of 200k cycles without any degradation was achieved on 128 RRAM devices by using programming pulses of 100 ns width.

Highlights

Resistive random access memory (RRAM) devices have gathered in recent years notable interest in the domain of future non-volatile memories (NVMs) [1]
The cumulative distribution functions (CDFs) of the current values measured during the set operation just after the target value is overcome are depicted in Figure 2b for the five different batches of 128 RRAM devices, each one assessed with one of the five pulse width values considered
No significant differences can be found among the five current CDFs with respect to the pulsed width employed for this preliminary programming stage

Summary

Introduction

Resistive random access memory (RRAM) devices have gathered in recent years notable interest in the domain of future non-volatile memories (NVMs) [1]. This technology is seen as a potential replacement of FLASH technology due to its high-density integration, fast switching, low-energy consumption, excellent endurance, long data retention and full compatibility with the CMOS fabrication flow [2,3]. In RRAM technology based on HfO2 insulators the resistance switching is based on the formation and disruption of nanometer scale conductive filaments (CFs), which are constituted by oxygen vacancies (VO ) [5]. In order to establish for the first time the CFs creating a closed route across the insulator, which connects the two metallic electrodes, a first stage, referred as forming operation, is required.

Methods

Results

Conclusion