Reset Operation Research Articles

Analysis on the Filament Structure Evolution in Reset Transition of Cu/HfO2/Pt RRAM Device.

The resistive switching (RS) process of resistive random access memory (RRAM) is dynamically correlated with the evolution process of conductive path or conductive filament (CF) during its breakdown (rupture) and recovery (reformation). In this study, a statistical evaluation method is developed to analyze the filament structure evolution process in the reset operation of Cu/HfO2/Pt RRAM device. This method is based on a specific functional relationship between the Weibull slopes of reset parameters’ distributions and the CF resistance (Ron). The CF of the Cu/HfO2/Pt device is demonstrated to be ruptured abruptly, and the CF structure of the device has completely degraded in the reset point. Since no intermediate states are generated in the abrupt reset process, it is quite favorable for the reliable and stable one-bit operation in RRAM device. Finally, on the basis of the cell-based analytical thermal dissolution model, a Monte Carlo (MC) simulation is implemented to further verify the experimental results. This work provides inspiration for RRAM reliability and performance design to put RRAM into practical application.

Reducing operation voltages by introducing a low-k switching layer in indium–tin-oxide-based resistance random access memory

In this letter, we inserted a low dielectric constant (low-k) or high dielectric constant (high-k) material as a switching layer in indium–tin-oxide-based resistive random-access memory. After measuring the two samples, we found that the low-k material device has very low operating voltages (−80 and 110 mV for SET and RESET operations, respectively). Current fitting results were then used with the COMSOL software package to simulate electric field distribution in the layers. After combining the electrical measurement results with simulations, a conduction model was proposed to explain resistance switching behaviors in the two structures.

Nanoscale Hafnium Oxide RRAM Devices Exhibit Pulse Dependent Behavior and Multi-level Resistance Capability

ABSTRACTResistive Random Access Memory (RRAM) is a novel form of non-volatile memory that is expected to play a major role in future computing and memory solutions. It has been shown that the resistance of RRAM devices can be precisely tuned by modulating switching voltages, by limiting peak current, and by adjusting the switching pulse duration. This enables the realization of novel applications such as memristive neuromorphic computing and neural network computing. The RRAM devices described in this work utilize an inert tungsten bottom electrode, hafnium oxide based active switching layer, a titanium oxygen exchange layer, and an inert titanium nitride top electrode. Linear sweep and controlled pulse (down to 10 ns) based electrical characterization of RRAM devices was performed in a 1 transistor 1 RRAM (1T1R) configuration to determine endurance, reliability, retention and threshold voltage parameters. We demonstrated endurance values above 108cycles with an average on/off ratio of 15 and pulse voltages for set/reset operation of ±1.5V. The on-chip 1T1R structures show an excellent controllability with respect to the low and high resistive state by manipulating the peak current from 75 up to 350µA we were able to achieve 10 discrete resistive states. Our results demonstrate that the set operation (which shifts the RRAM device from the high to the low resistance state) is only dependent on the voltage of the switching pulse and the peak current limit. The reset operation, however, occurs in an analog fashion and appears to be dependent on the total energy of the applied switching pulse. Pulse energy was modulated by varying the peak voltage which resulted in a larger relative change of the RRAM device resistance.

Analysis of Subthreshold Current Reset Noise in Image Sensors.

To discuss the reset noise generated by slow subthreshold currents in image sensors, intuitive and simple analytical forms are derived, in spite of the subthreshold current nonlinearity. These solutions characterize the time evolution of the reset noise during the reset operation. With soft reset, the reset noise tends to when , in full agreement with previously published results. In this equation, is the photodiode (PD) capacitance and m is a constant. The noise has an asymptotic time dependence of , even though the asymptotic time dependence of the average (deterministic) PD voltage is as slow as . The flush reset method is effective because the hard reset part eliminates image lag, and the soft reset part reduces the noise to soft reset level. The feedback reset with reverse taper control method shows both a fast convergence and a good reset noise reduction. When the feedback amplifier gain, A, is larger, even small value of capacitance, , between the input and output of the feedback amplifier will drastically decrease the reset noise. If the feedback is sufficiently fast, the reset noise limit when , becomes in terms of the number of electron in the PD. According to this simple model, if CPD = 10 fF, CP/CPD = 0.01, and A = 2700 are assumed, deep sub-electron rms reset noise is possible.

Titanium-Oxide-Based Slot Contact RRAM in Nanoscaled FinFET Logic Technologies

In this letter, a new ultrahigh-density memory constructed with a contact resistive random access memory (RRAM) is proposed. This slot contact RRAM (SCRRAM) with transition metal oxide from contact liner layers has been successfully demonstrated by a standard 16-nm FinFET process without extra mask or processing step. The new FinFET RRAM features low-power forming and reset operation, stable Low Resistance State (LRS)/High Resistance State (HRS), and compact cell size. As a logic nonvolatile memory (NVM) solution, SCRRAM exhibits high endurance, stable data retention, read and program disturb immunity, which further support this new 1T1R cell as one of the promising embedded NVM solutions in FinFET CMOS generations.

Superlattice-like film for high data retention and high speed phase change random access memory

Superlattice-like film (SLF) was formed alternately by Ti0.43Sb2Te3 (TST) and TiN, and TST is employed as phase change layers and TiN is employed as isolation layers of TST film. Comparing with single TST film with the same thickness, SLF owns higher data retention, higher phase change speed (5ns) and endurance up to 1×105 cycles, and its power consumption of reset operation is significantly decreased by 65.2%. Two-dimensional thermal transient simulation of reset operation indicates that SLF-based device owns higher heating efficiency than 30-nm-thick TST-based device.

Laterally configured resistive switching device based on transition-metal nano-gap electrode on Gd oxide

We have developed a fabrication process for a laterally configured resistive switching device based on a Gd oxide. A nano-gap electrode connected by a Gd oxide with the ideal interfaces has been created by adapting the electro-migration method in a metal/GdOx bilayer system. Bipolar set and reset operations have been clearly observed in the Pt/GdOx system similarly in the vertical device based on GdOx. Interestingly, we were able to observe a clear bipolar switching also in a ferromagnetic CoFeB nano-gap electrode with better stability compared to the Pt/GdOx device. The superior performance of the CoFeB/GdOx device implies the importance of the spin on the resistive switching.

Interface-induced two-step RESET for filament-based multi-level resistive memory

In this paper, a two-step RESET switching behavior of Ag/Al2O3/HfO2/Pt bilayer resistive random access memory (RRAM) devices is investigated. The interface between the two oxide layers is responsible for the special two-step RESET switching. When the conducting filaments have ruptured in the lower layer, the interface can protect the Ag ions of the filaments from breaking in the upper layer due to the trapped charges or defects at the interface. Therefore, a stable middle resistance state (MRS) is realized and the device exhibits a terrace-like I–V curve during the RESET operations. A filament-based switching mechanism combined with the electron hopping theory is proposed to explain the physical nature of the two-step RESET behavior. Furthermore, a good multi-level resistive switching performance with excellent endurance and retention reliability is obtained.

Multi-component machine repair problem with unreliable repairman, reboot, imperfect recovery and retrial

The present study aims at the performance prediction of a multi-component machining system comprised of operating and mixed warm standby units under the care of a single unreliable server and retrial attempts. The concepts of reboot and recovery are incorporated to portray the real time manufacturing/production system dealing with automatic machines. A failed unit is automatically detected and fixed with a coverage probability. In case of unsuccessful recovery, the fault is cleared by reboot or reset operation. If the server is in idle state, the person taking care of the failed units joins the orbit and retries again and again for the repair of the failed units. To explore the transient state behaviour of the machine repair system, we establish various performance measures in terms of transient state probabilities of the number of failed units present in the system. Further, a comparative analysis of performance measures is presented for different system configuration. The feasibility of implementation of soft-computing technique is explored by computing the performance measures using adaptive network-based fuzzy interference systems (ANFIS).

Editors' Choice Communication—Hourglass-Shaped Metal-Filament Switching Device with Multi-Layer (AlOX/TiO2) Oxide Electrolytes

This paper proposes using hourglass-shaped metal filaments to improve the ON/OFF resistance ratio and retention characteristics of switching devices used in reconfigurable logic applications. These filaments are obtained by controlling the Cu-ion mobility in multi-layer oxide electrolytes. By adopting an upper AlOX and lower TiO2 electrolyte layers with respectively low and high Cu-ion mobility, we could form hourglass-shaped filaments as a result of suppressed Cu-ion injection and enhanced filament lateral growth. The hourglass-shaped metal filaments induced local Joule heating at the filament constriction, thus accelerating RESET operations. We confirmed that, as a result, Cu/AlOX/TiO2/W devices show high ON/OFF resistance ratios (>106) and ∼10-year retention properties at 80°C.

Analysis on the Ramp Reset Operation by Measuring the Surface Charge Distribution in an ac PDP Cell

We measured the spatiotemporal surface charge distribution in a co-planar type alternating current plasma display panel driven by the ramp type reset waveform. The longitudinal electro optic modulation technique with BSO single crystal was used to measure the surface charge density. The result shows that the surface charge distributions on sustain and address electrodes after reset period are almost same independent of the initial conditions which are result from the sustain discharge at previous subfield. The result also shows that the discharge during the ramp type reset waveform is mainly occurred at near gap between sustain electrodes. During the ramp reset discharge.

Ge2Sb2Te5/Sb superlattice-like thin film for high speed phase change memory application

In order to improve the operation speed of phase change memory (PCM), superlattice-like Ge2Sb2Te5/Sb (SLL GST/Sb) thin films were prepared in a sputtering method to explore the suitability as an active material for PCM application. Compared with GST, SLL GST/Sb thin film has a lower crystallization temperature, crystallization activation energy, thermal conductivity, and smaller crystalline grain size. A faster SET/RESET switching speed (10 ns) and a lower operation power consumption (the energy for RESET operation 9.1 × 10−13 J) are obtained. In addition, GST/Sb shows a good endurance of 8.3 × 104 cycles.

Switching operation and degradation of resistive random access memory composed of tungsten oxide and copper investigated using in-situ TEM

In-situ transmission electron microscopy (in-situ TEM) was performed to investigate the switching operation of a resistive random access memory (ReRAM) made of copper, tungsten oxide and titanium nitride (Cu/WOx/TiN). In the first Set (Forming) operation to initialize the device, precipitation appeared inside the WOx layer. It was presumed that a Cu conducting filament was formed, lowering the resistance (on-state). The Reset operation induced a higher resistance (the off-state). No change in the microstructure was identified in the TEM images. Only when an additional Reset current was applied after switching to the off-state could erasure of the filament be seen (over-Reset). Therefore, it was concluded that structural change relating to the resistance switch was localized in a very small area around the filament. With repeated switching operations and increasing operational current, the WOx/electrode interfaces became indistinct. At the same time, the resistance of the off-state gradually decreased. This is thought to be caused by Cu condensation at the interfaces because of leakage current through the area other than through the filament. This will lead to device degradation through mechanisms such as endurance failure. This is the first accelerated aging test of ReRAM achieved using in-situ TEM.

SnSb4/SiO2 multilayered thin films for phase change memory applications

SnSb4/SiO2 (SS/SiO2) multilayer thin films were prepared by using a radio-frequency (RF) magnetron sputtering method. The amorphous-to-crystalline transitions of SS/SiO2 films were investigated by in situ film resistance measurements. The thermal stability of amorphous SS thin films was greatly improved by the addition of SiO2. However, the thermal conductivity of SS/SiO2 multilayer thin films (0.23W/(m·K)) was much lower than that of monolayer SS thin film (1.37W/(m·K)). The result of X-ray diffractomer (XRD) measurement indicated that excess Sb composition existed in SS/SiO2 multilayer thin films, which could accelerate the phase change of the material. The multilayer configuration of SS/SiO2 multilayer thin film before and after crystallization was confirmed by transmission electron microscopy (TEM). Phase change memory (PCM) devices based on [SS(2nm)/SiO2(1.5nm)]14 thin film were fabricated and the low power consumption for the RESET operation was achieved (7.8×10−12J), which was significantly lower than that of GST cell (2.6×10−9J).

Experimental and theoretical analysis of Landauer erasure in nano-magnetic switches of different sizes

Bistable nano-magnetic switches are extensively used in storage media and magnetic memories, associating each logic state to a different equilibrium orientation of the magnetization. Here we consider the issue of the minimum energy required to change the information content of nano-magnetic switches, a crucial topic to face fundamental challenges of current technology, such as power dissipation and limits of scaling. The energy dissipated during a reset operation, also known as “Landauer erasure”, has been accurately measured at room temperature by vectorial magneto-optical measurements in arrays of elongated Permalloy nanodots. Both elliptical and rectangular dots were analysed, with lateral sizes ranging from several hundreds to a few tens of nanometers and thickness of either 10nm or 5nm. The experimental results show a nearly linear decrease of the dissipated energy with the dot volume, ranging from three to one orders of magnitude above the theoretical Landauer limit of kBT×ln(2). These experimental findings are corroborated by micromagnetic simulations showing that the significant deviations from the ideal macrospin behavior are caused by both inhomogeneous magnetization distribution and edge effects, leading to an average produced heat which is appreciably larger than that expected for ideal nanoswitches.

Electrical characterization and modeling of pulse-based forming techniques in RRAM arrays

The forming process, which corresponds to the activation of the switching filament in Resistive Random Access Memory (RRAM) arrays, has a strong impact on the cells’ performances. In this paper we characterize and compare different pulse forming techniques in terms of forming time, yield and cell-to-cell variability on 4kbits RRAM arrays. Moreover, post-forming modeling during Reset operation of correctly working and over formed cells has been performed. An incremental form and verify technique, based on a sequence of trapezoidal waveforms with increasing voltages followed by a verify operation that terminates when the expected switching behavior has been achieved, showed the best results. This procedure narrows the post-forming current distribution whereas reducing the Reset switching voltage and the operative current. These advantages materialize in a better control of the cell-to-cell variability and in an overall time and energy saving at the system level.

Set and Reset Voltage Interdependence in Resistive Switching Memory Cells

A statistical correlation between set voltage, Vset, and the preceding reset voltage, Vreset, has been observed on a multitude of devices in a resistive RRAM memory array. This correlation can be reproduced on a single device by generating a spread in Vreset values by varying the linear voltage ramp rate during the reset operation. The dependence of Vreset on voltage ramp rate is modeled successfully by assuming a fixed critical Joules heat required to trigger the rupture of the filament. The observed dependence of Vset and Vreset on the voltage ramp rate may be used to tighten Vset and Vreset distributions, by applying during the reset operation low voltage ramp rates to cells with high Vset and high ramp rates to cells with low Vset values.

Low‐current operation of novel Gd2O3‐based RRAM cells with large memory window

In this paper, we introduce rare‐earth hygroscopic oxide Gd2O3 as a novel switching material allowing extended reset operation as compared to standard state‐of‐the‐art oxide like (Hf,Al)O2. We prepared 5 nm‐thick oxide layers, as integrated between TiN and Hf electrodes in 1‐transistor/1‐resistor configuration. Using industry‐relevant programming current I ≤ 10 µA and pulse width ≤1 µs, 40 nm‐size TiN\Gd2O3\Hf cells allowed reaching a median memory window (MW) > × 70 while state‐of‐the‐art materials exhibited MW < × 10 in the same conditions. Based on the large MW, high write endurance properties (>106 cycles), and good retention of Gd2O3‐based cells (>5 days at 85 °C), verify algorithms allow reliable programming with low latency.

Write and Erase Threshold Voltage Interdependence in Resistive Switching Memory Cells

A statistical dependence of set voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">set</sub> on the preceding reset voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">reset</sub> is observed in resistive memory arrays and explained in terms of two interlocking mechanisms. This dependence can be replicated on a single device by intentionally varying V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">reset</sub> values by various linear voltage ramp rates. The latter mechanism is well modeled under the assumption that a critical heat deposited locally in the filament triggers the rupture of the filament. Mechanisms are proposed to explain the impact of different ramp rates of the reset operation on the ruptured gap in the filament that affect, in turn, the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">set</sub> value of the subsequent set operation. Based on these observations, a one-time tightening procedure is designed, leading to tightened V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">set</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">reset</sub> distributions.

Design of Positive Edge Triggered D Flip-FlopUsing 32nm CMOS Technology

The usage of the low power consumptions devices in today’s global village has become pervasive and indispensable in almost every walk of life. The thrust is towards reducing the high power energy consumption, required to reduce cost of the circuitry, while increasing the speed of performances in any operations. A high speed low power consumption positive edge triggered Delayed (D) flip-flop can be design for increasing the speed of counter in Phase locked loop, using 32 nm CMOS technology. Here we design D flip-flop for Phase locked loop (PLL). Phase locked loop is an important analog circuit used in various communication applications such as frequency synthesizer, radio computer, clock generation microprocessors etc. The design counter can be used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The propose circuit will faster than conventional circuit as it will have fast reset operation. The circuit will consumes less power as it prevents short circuit power consumption. The circuit operates at low voltage power supply. The CMOS based fast D flip-flop circuit can be design and simulated by using Microwind 3.1 tool.