Reliability Of Solder Interconnects Research Articles

Study of migration and coalescence of voids driven by electric current stressing in solder interconnects using phase field simulation

Voids in solder interconnects play a crucial role in influencing performance and reliability of solder interconnects, and even lead to the open failure of electronics, especially when high density electric current flowing through the solder interconnects. In this paper, the morphological evolution and migration behaviour of the voids in the solder domain of solder interconnects under electric current stressing is investigated using a developed phase field model. Results show that the surface energy drives the coalescence of voids, and large size voids grow up at the expense of small size ones. The voids migrate along the electric current direction, and the current density distribution and void distribution interactively affect the evolution and migration of the voids. The high magnitude of electric field can potentially induce the open-circuit failure, and the void size is affected by the electric field. Moreover, the voltage across the solder domain increases as the voids migrate to the cathode side. Furthermore, the electric field can promote the void coarsening, and the void migration velocity increases almost linearly with the magnitude of the electric field.

Accelerated Solder Interconnect Testing Under Electromigratory and Mechanical Strain Conditions

Abstract Continuous power density increases and interconnect scaling in electronic packages raises risk of electromigration (EM) induced failures in high current interconnects. Concurrently, thermal cycling fatigue also places interconnects at risk of reliability failure during electronics' operating lifetime. These two differing failure mechanisms are historically treated separately, but in operation, the combination of EM effects and thermal cycling can act synchronously in accelerating failure. Presently, there is no model to predict the complexity of reliability estimation arising from these interacting failure modes but is certainly important for high current density applications. In this work, a novel testing system has been employed to facilitate the estimation of the reliability of solder interconnects under the combined influence of EM and mechanical strain. The system subjects solder interconnects to high current density, elevated ambient temperature, and a constant tensile stress while recording the change in electrical resistance and change in length of the solder over time. The solder samples were created using two copper wires connected by a eutectic Pb/Sn solder ball to imitate flip-chip or BGA packaging interconnects, allowing for controlled testing conditions in order to demonstrate the combined effects of a mechanical load and EM on the lifetime of a solder joint. A significant reduction in lifetime was observed for samples that endured the coupled accelerating factors. Comparing the experimental results of different current densities at different stress levels provided a new outlook on the nature of coupled failure acceleration in solders. This novel test methodology can inform model generation for better anticipating the failure rate of solder interconnects which naturally experience multiple stress inputs during their lifetime.

Shear performance and accelerated reliability of solder interconnects for fan-out wafer-level package

As the packaging density in wafer-level packaging increases, there is an increasing need for packaging processes for fan-out packaged devices; thus, the soldering reliability of board-level devices is particularly important. Fan-out wafer-level packaging (FOWLP) is typically packaged using flip-chip methods on Cu electrodes and printed circuit board (PCB) substrates. Therefore, in this study, we designed new PCBs based on a 6 × 4 mm2 FOWLP test vehicle with an electroless nickel gold (ENIG) surface finish. After optimizing 21 bonding parameters (temperature, holding time, and shear strength), the ideal bonding parameter was achieved at 260 °C for 10 s. We also found that the ENIG pads were dissolved in solder joints at conditions above 270 °C for 10 s, causing the pads to break away from the PCB and the solder joint failure. As a result, the mechanical properties of the joints declined. Under long high-temperature durations, the molten Sn bypassed the Ni layer, flowed into the bottom of the pad, and reacted with Cu, causing volume shrinkage of the solder joints and the pads to break away from the PCB.

Effect of high current pulses on solder interfacial reaction and interconnect reliability

The trend of electrification and miniaturization brings the reliability of interconnects to the forefront. The solder joints are subjected to thermo-mechanical mismatch due to the Joule heating and electromigration (EM)-induced degradation under high current stressing conditions. However, most of the studies are limited to lab test samples or lab test conditions, which lack transferability in engineering applications. In this paper, automotive electronic components are studied subjected to field-like current pulse conditions. The work aims to understand the field-relevant failure modes of solder joints exposed to high current stressing via experimental and numerical investigations. Shunt components with and without Ni plating are analyzed in power cycling tests. A polarity effect is observed in the growth of intermetallic compounds (IMCs). The thickness of IMC at the anode exhibits an approximately linear growth with current stressing time, whereas the thickness of IMC at the cathode remains almost unchanged or slightly decreased. Ni, as diffusion barrier, serves to restrain Cu consumption from the terminals of shunts and also reduces Cu mass transport into and within the solder. The net Cu flux at the interface and in the solder is discussed to analyze the IMC growth kinetics. The shunts with Ni plating undergo less EM of Cu and yield longer lifetime. Voids and crack formation are detected in computer tomography (CT) scans and cross-sectional analysis by scanning electron microscopy (SEM). Finite element method (FEM) is implemented to simulate thermo-electro-mechanical fields of the assembly under power cycling test conditions. The distribution of divergence of material flux density corresponds well with the location of voids formation and provides good estimation for the lifetime.

Modelling and analysis of vibration on power electronic module structure and application of model order reduction

Modelling and analysis of vibration of an IGBT power electronic module (PEM) structure were undertaken. PEM structure considered in this study was without molding compound and wirebonds. The most critical resonant frequency was identified by modal analysis. At the critical frequency of 1345 Hz, for the vertical displacement of the base excitation, subsequent stress distribution on the PEM structure was analysed. Concurrent vibration and thermo-mechanical fatigue loads on the reliability of PEM structure solder interconnects were also estimated by widely used linear damage superposition approach. It was concluded that the at critical resonant frequency the vibration induced damage is more severe than the thermo-mechanical fatigue loading. In addition, a quarter car model (QCM) was used to mimic the dynamic interaction between the rough road surface and an electric vehicle (EV) in order to analyse the road surface roughness induced excitation on the PEM structure in the engine compartment. Stress and strain distribution on the PEM structure due to road surface roughness were analysed. Furthermore, three Krylov subspace based model order reduction (MOR) techniques were applied to the resulting dynamic system in vibration analysis. Due to the limits on computing resources, a submodel was utilized for MOR analysis. Within the three MOR techniques, Passive Reduced order Interconnect Macromodeling Algorithm (PRIMA) MOR technique performs better than the other techniques. Computational time ratio between reduced system iteration and the full system iteration is 1: 53.

Thermomechanical Analysis of Conformally Coated QFNs for High-Reliability Applications

The use of quad flat no-leads (QFNs) in high-reliability applications is receiving increased interest. To address concerns of harsh working environments, conformal coatings are used to protect the components and associated printed circuit board (PCB). However, using conformal coatings can pose a reliability risk for the components on the PCB. This paper details an investigation into the effect of conformal coatings on the reliability of QFN second-level solder interconnections. Five QFN package types and two types of conformal coatings were investigated. In the experiments, a large population of QFN assemblies coated with conformal coatings were subjected to a thermal cycling test condition. These components, designed with daisy-chain connections, were monitored during the thermal cycling tests, and the exact time for failure to occur for each component was recorded and analyzed. Detailed finite-element models for the tested QFN assemblies were developed; the inelastic strain energy density was used as the damage indicator to evaluate the impact of conformal coating on the solder joint reliability. Modeling results reveal that the conformal coating plays an intricate role in QFN solder joint reliability. The presence of conformal coating results in a reduction in the shear stress in the solder joint and plays a positive role in solder reliability. However, it also induces more stress in the solder joint in the out-of-plane direction and plays a negative role. These two mechanisms are competing, and their relative magnitude will determine the overall effect of conformal coating on solder joint reliability.

The Architecture Design and Novel Material Selection for Improved Reliability of Solder Interconnections in Microelectronic Packaging

This study focused on the materials issues and related reliability testing on Cu-core solder joints for power device, low temperature solder joints for flexible substrate and the utilization of Cu-Zn under-bump metallization (UBM) in micro-BGA solder joints. The fabrication of electrodeposited Cu-Zn metallization is also demonstrate. The future prospect and challenge for the material system and the reliability issues in microelectronic packaging are also addressed.

Development of a Simplistic Method to Simulate the Formation of Intermetallic Compounds in Diffusion Soldering Process

A simplistic simulation technique has been developed for computing the individual intermetallic compound (IMC) thickness which is formed in substrate-solder (Cu-Sn) systems during the diffusion soldering process in high-temperature power electronic applications. The method requires the time-dependent temperature profile for the soldering process and the growth rate parameters (e.g. concentration gradient, diffusion coefficient, activation energy, etc.) for the development of IMC layers as input. The method is suitable for predicting the thickness of an intermetallic phase layer during the diffusion soldering process. As such, it can be used in high-temperature power electronic application’s solder processing to enhance the reliability and lifetime of solder interconnections by allowing the control of the thickness of IMC layers. The method is demonstrated for IMC growth between pure copper as substrate and pure Sn as solder material. The growth behavior of the IMC layer is increased with increasing temperature over time according to the Arrhenius theory in the temperature range between 24°C to 260°C. To simulate the formation of IMC thickness in diffusion soldering interconnections, a simplistic way has been attempted using the popular commercial finite element simulation tool Comsol Multiphysics and scientific computing application ‘Matlab’. By means of transient thermal input, the diffusion-controlled intermetallic phase formation is simulated here. Few assumptions are taken care of this simulation process, for example, no convection, no reaction, solid-solid diffusion, no the pressure effect on the computational domain.

Impact of underfill and other physical dimensions on Silicon Lateral IGBT package reliability using computer model with discrete and continuous design variables

An effort to design and build a prototype LED driver system which is energy efficient, highly compact and with few component count was initiated by a consortium UK universities. The prototype system will be based on Silicon Lateral IGBT (LIGBT) device combined with chip on board technology. Part of this effort, finite element modelling and analysis were undertaken in order to mitigate the underfill dielectric breakdown failure and solder interconnect fatigue failure of the LIGBT package structure. Electro-static analysis was undertaken to predict the extreme electric field distribution in the underfill. Based on electro-static analysis, five commercial underfill were selected for thermo-mechanical finite element analysis on solder joint fatigue failure prediction under cyclic loading. A design optimisation analysis was endeavoured to maximise the solder interconnect reliability by utilising a computer model with continuous variable (physical dimensions) and discrete variables (underfill type) and a stochastic optimiser such as multi-objective mixed discrete particle swarm optimisation. From the optimisation analysis best trade off solution are obtained.

Research on microstructure and mechanical behaviour of smaller microbumps for high density solder interconnects

PurposeThe purpose of this paper is to study the microstructure and mechanical behaviour of smaller microbumps for high density solder interconnects.Design/methodology/approachThe microstructure was analyzed by scanning electron microscopy and electron backscatter diffraction tests to determine the Sn grain number of the resultant microbumps. The nanomechanical properties of Sn microbumps were investigated by the nanoindentation and shearing tests to understand the failure mechanism and assess the reliability of ultra-high density solder interconnects with numbered grains.FindingsOnly one Sn grain is observed in the interconnect matrix when the microbumps are miniaturized to 40 μm or less. Because of the body-centred tetragonal lattice of ß-Sn unit cell, the mechanical properties of the one-grain Sn microbumps are remarkably anisotropic, which are proved by the difference of the elastic modulus and the stiffness in the different orientations. The shearing tests show that the one-grain Sn microbump has a typical brittle sliding fracture of monocrystal at different shearing speeds.Practical implicationsThe paper provides a comparable study for the performance of the bigger solder joints and also makes preliminary research on the microstructure and mechanical behaviour of Sn microbumps with the diameter of 40 μm.Originality/valueThe findings in this paper provide methods of microstructure study by combination of EBSD test and metallographic analysis, mechanical study by combination of nanoindentation test and shearing test, which can provide good guidelines for other smaller microbumps. The strain rate sensitivity exponent of the one-grain Sn microbumps is consistent with the Pb-free bulk solder. This implies that the one-grain Sn microbump has a comparable flow stress to Sn37Pb solder, which is beneficial for Pb-free replacement in higher density microelectronic packaging.

Microstructural Evolution and Migration Mechanism Study in a Eutectic Sn-37Pb Lap Joint Under High Current Density

The microstructural evolution in eutectic Sn-37Pb solder under high current density seriously threatens the reliability of solder interconnections, but atomic electromigration has often been confused with thermomigration. In this paper, after decoupling the effect of the non-uniform temperature distribution in a Cu/Sn-37Pb/Cu lap joint from the current stress, the microstructural evolution was investigated under an average current density of 1.84 × 104 A cm−2 for 0–24 h. The decomposition and recombination of the Pb-rich phase occurred at the cathode and the anode, respectively. The corresponding migration mechanism was proposed from the viewpoint of energy and was explained by the interactions among the potential energies of ripening, electron wind force, and back stress. Our study may be helpful for understanding the migration mechanism and reliability of eutectic two-phase solder joints and provides supporting data for interpreting the acceleration tests of Sn-37Pb solder joints under electromigration.

Effect of elevated temperature on PCB responses and solder interconnect reliability under vibration loading

In this paper, vibration tests are conducted to investigate the influence of temperature on PCB responses. A set of combined tests of temperature and vibration is designed to evaluate solder interconnect reliability at 25°C, 65°C and 105°C. Results indicate that temperature significantly affects PCB responses, which leads to remarkable differences in vibration loading intensity. The PCB eigenfrequency shifts from 290Hz to 276Hz with an increase of test temperature from 25°C to 105°C, during which the peak strain amplitude is almost the same.Vibration reliability of solder interconnects is greatly improved with temperature rise from 25°C to 105°C. Mean time to failure (MTTF) of solder joint at 65°C and 105°C is increased by 70% and 174% respectively compared to that of solder joint at 25°C. Temperature dominates crack propagation path of solder joint during vibration test. Crack propagation path is changed from the area between intermetallic compound (IMC) layer and Cu pad to the bulk solder with temperature increase.

Assessment of Joint Reliability of Sn–2.5Ag–0.5Cu Solder/Cu as a Function of Reflow Time

Solder interconnect reliability is exceedingly influenced by the solder material properties, the intermetallics formed during soldering, and the environmentally imposed loads. The current study involves the study of the wetting behaviour, interfacial reactions and growth of intermetallic compounds (IMCs) in Sn–2.5Ag–0.5Cu lead free solder solidified on Cu substrate as function of reflow time. The reflow temperature was maintained at 270 °C and reflow time was varied from 10 to 10,000 s. The solder alloy showed better wettability on the substrate with the increase in reflow time. A growth in Cu6Sn5 IMC thickness was observed up to a reflow time of 500 s. IMC layer formed during a reflow time of 10 s was 3.09 μm and its thickness increased to 4.40, 8.21, 10.96 μm during 100, 300 and 500 s reflow time respectively. A decrease in the thickness of IMC was observed for samples reflowed for 1000 s. The IMC thickness increased with further increase in reflow time. The joint reliability of Sn–2.5Ag–0.5Cu solder solidified on copper substrate surfaces was assessed by performing bond shear test. The average shear strength decreased with an increase in reflow time after an optimum value.

Effect of Aluminium and Silicon to IMC Formation in Low Ag-SAC Solder

The effect of Al and Si addition on IMC formation at the solder and Cu substrate interface was investigated. The compositions of the solder alloy used are Sn-0.3 wt.% Ag-0.5 wt.% Cu (SAC0305), SAC0305-1 wt.% Al (SAC0305-1Al), SAC0305-2 wt.% Al (SAC0305-2Al) and SAC0305-2 wt.% Al-2 wt.% Si (SAC0305-2Al-2Si). Solder alloys were prepared by casting process. Melting temperature of each solder alloys was determined using DSC. Reflow process of the solder alloys were carried out at 260 oC on Cu substrate. Morphology of the intermetallic compound (IMC) formed at the solder joint was observed using Fe-SEM equipped with EDX. The addition of Al and Si reduced the thickness of IMC layer formed at the solder joint. The addition of 1.0 wt.% Al formed planar shape of IMC while the addition of 2.0 wt.% Al and 2.0 wt.% Al with 2.0 wt.% Si formed scallop shape of IMC. This is due to Cu-Al IMC and Ag-Al IMC scattered near the interface that act as diffusion barriers to Sn diffusion. This suggests that the addition of right amount of Al and Si could form thinner IMC layer that could lead to increase of reliability of solder interconnect.

Electrodeposition and Characterisation of Novel Ni-NbOx Composite Coatings as a Diffusion Barrier for Liquid Solder Interconnects - Part II: Diffusion Barrier Performance

The control of interfacial microstructural stability is of utmost importance to the reliability of liquid solder interconnects in high temperature electronic assemblies. This is primarily due to excessive intermetallic compounds (IMCs) that can form and continuously grow during high temperature operation, which renders conventional barrier metallisations inadequate. With the intention of reducing such excessive IMC growth, electrically conducting, NbOx containing Ni coatings were developed using electrodeposition and were assessed as solder diffusion barrier layers in terms of their electrical conductivity and barrier property. The present work adopts a novel electrochemical route to produce Ni-NbOx composite coatings of good uniformity, compactness and purity, from non-aqueous glycol-based electrolytes consisting of NiCl2 and NbCl5 as metal precursors. The effects of cathodic current density and NaBH4 concentrations on the surface morphology, composition and thickness of the coatings were examined. Increased NaBH4 concentrations were found to elevate the maximum deposit thickness (above 10 µm), although these led to a reduction in the co-deposited Nb content. The composite coatings generally exhibited good electrical conductivity. The reaction between a liquid 52In-48Sn solder and Ni-NbOx, with Nb contents up to 6 at.%, was studied at 200ºC. The results indicate that, Ni-NbOx with sufficient layer thickness and higher Nb content, offered longer service lifetime. Nb enrichment was generally observed at or close to the reaction front after high temperature storage which suggests evident effectiveness of the enhanced diffusion barrier characteristics. A mechanism for the role of Nb as a barrier performance enhancer was postulated.

Diffusion Barrier Characteristics of Ni-NbOx Composite Electrodeposits for Liquid In-Sn Solder Interconnects

The control of interfacial microstructural stability is of utmost importance to the reliability of liquid solder interconnects in high temperature electronic assemblies. This is primarily due to excessive intermetallic compounds (IMCs) that can form and continuously grow during high temperature operation, which renders conventional barrier metallizations inadequate. With the intention of reducing such excessive IMC growth, electrically conducting, NbOx containing Ni coatings were developed using electrodeposition and were assessed as solder diffusion barrier layers in terms of their electrical conductivity and barrier property. The present work adopts a novel electrochemical route to produce Ni-NbOx composite coatings of good uniformity, compactness and purity, from non-aqueous glycol-based electrolytes consisting of NiCl2 and NbCl5 as metal precursors. The effects of cathodic current density and NaBH4 concentrations on the surface morphology, composition and thickness of the coatings were examined. Increased NaBH4 concentrations were found to elevate the maximum deposit thickness (above 10 μm), although these led to a reduction in the co-deposited Nb content. The composite coatings generally exhibited good electrical conductivity. The reaction between a liquid 52In-48Sn solder and Ni-NbOx, with Nb contents up to 6 at.%, was studied at 200°C. The results indicate that, Ni-NbOx with sufficient layer thickness and higher Nb content, offered longer service lifetime. Nb enrichment was generally observed at or close to the reaction front after high temperature storage which suggests evident effectiveness of the enhanced diffusion barrier characteristics. A mechanism for the role of Nb as a barrier performance enhancer was postulated.

Strain behaviors of solder bump with underfill for flip chip package under thermal loading condition

Since the introduction of Cu/low-k as the interconnect material, the chip-package interaction (CPI) has become a critical reliability challenge for flip chip packages. Revision of underfill material must be considered, which compromises the life of flip chip interconnect by releasing the stresses transferred to the silicon devices from the solder bumps, and thereby maintain the overall package reliability. Thus, it is important to understand the thermo-mechanical behavior of solder bumps. In this study, the solder bump reliability in flip chip package was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermo-mechanical behavior of solder joints, especially the solder bumps located at the chip corners where most failures usually occur was investigated. Digital image correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of cross-sectioned solder bump of flip-chip package subjected to thermal loading from 25°C to 100°C. The results clearly show captured deformations of solder bump under thermal loading. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments, and validated with experimental results. Then, consistently using the FEA analysis, parametric study for underfill material properties were performed on the reliability of flip chip package, by varying the glass transition temperature (Tg), Young’s modulus (E), and coefficient of thermal expansion (CTE). Averaged plastic work of the corner solder bump and stress at the die side were obtained and used as damage indicators for solder bumps and low-k dielectrics layer, respectively. The results show that high Tg, and E of underfill are generally desirable to improve the reliability of solder interconnects in the flip chip package.

In situ study on reverse polarity effect in Cu/Sn–9Zn/Ni interconnect undergoing liquid–solid electromigration

Synchrotron radiation real-time imaging technology was used to in situ study the interfacial reactions in Cu/Sn–9Zn/Ni solder interconnects undergoing liquid–solid electromigration (L–S EM). The reverse polarity effect, evidenced by the continuous growth of intermetallic compound (IMC) layer at the cathode and the thinning of the IMC layer at the anode, was resulted from the abnormal directional migration of Zn atoms toward the cathode in electric field. This abnormal migration behavior was induced by the positive effective charge number (Z∗) of Zn atoms, which was calculated to be +0.63 based on the Cu fluxes and the consumption kinetics of the anode Cu. Irrespective of the flowing direction of electrons, the consumption of Cu film was obvious while that of Ni film was limited. The dissolution of anode Cu followed a linear relationship with time while that of cathode Cu followed a parabolic relationship with time. It is more damaging with electrons flowing from the Ni to the Cu than that from the Cu to the Ni. The simulated Zn concentration distributions gave an explanation on the relationship between abnormal migration behavior of Zn atoms and the dissolution of Cu film under electron wind force. The abnormal directional migration of Zn atoms toward the cathode prevented the dissolution of cathode substrate, which is beneficial to improve the EM reliability of micro-bump solder interconnects.

Physics-of-failure assessment methodology for power electronic systems

Driven by consumer markets and industrial needs, power electronic systems are operating at higher power densities, in smaller packages and in more exotic environments. As these trends continue, ensuring long-term operation in harsher conditions requires accurate reliability prediction models, most viably obtained through Physics-of-Failure (PoF) methodologies. This paper introduces a PoF-based system-level reliability assessment procedure in which the dominant failure mechanisms are identified for three primary subsystems: the power module, DC-link capacitors and the control circuitry. This report outlines the dominant failure modes and mechanisms for each subsystem and provides examples of how to improve subsystem reliability based upon the described assessment methodology. A case study is also presented in which the solder interconnect reliability of the gate-driver board in a mid-range variable frequency drive (VFD) was assessed.

Drop Impact Reliability Analysis of 3-D Chip-on-Chip Packaging: Numerical Modeling and Experimental Validation

This paper aims at investigating the drop impact solder interconnect reliability of an advanced ultra-fine-pitch 3-D integrated circuit chip stacking packaging in accordance with JEDEC board-level test specification through finite-element (FE) simulation and experimental testing. To characterize the transient dynamic responses of the package, ANSYS/LS-DYNA incorporated with the Input-G method is applied. To well simulate the mechanical behaviors of the solder interconnects, a strain-rate-dependent elastoplastic Johnson-Cook constitutive model for the Sn3.5Ag solder is applied. In addition, an inverse calculation is carried out to identify the overall structural damping of the dynamic system. Furthermore, a JEDEC-compliant drop tester is used to conduct the drop test, where failure analysis is performed using an optical microscope. Moreover, a simplified Darveaux fatigue life prediction model is constructed based on the calculated strain energy densities at different JEDEC test conditions together with the corresponding drop test data. To demonstrate the validity of the developed fatigue life prediction model, a confirmatory experiment is performed. Finally, parametric FE study incorporated with experimental design is performed to seek a design guideline for enhanced solder interconnect reliability under drop impact. Both the experimental and simulation data reveal that underfill can greatly enhance the drop impact reliability of the solder interconnects. In addition, the cornered interconnects and even package in a one-component configuration would fail earlier than the central ones, with a cohesive fracture in the Sn3.5Ag solder rather than the intermetallic compound (IMC) and its interface. Besides, an increasing IMC thickness reduces the drop impact solder interconnect reliability while enhancing the thermal cycling one.