Reflow Technology Research Articles

Overview of Different Approaches in Numerical Modelling of Reflow Soldering Applications

This paper gives a review of different applications in the numerical modelling of reflow soldering technology from recent years. The focus was on detailing the different process types, the physical background, and related mathematical models. Reflow soldering is the main connection technology of surface mounting. Firstly, the solder in paste form is stencil-printed onto the solder pads of the applied substrate, and then surface mounted devices are placed onto the solder deposits. Finally, the whole assembly is heated over the melting temperature of the solder alloy, which melts and forms solder joints. Surface mounting technology needs a low defect rate which is determined by process parameters, material properties, and the printed circuit board design. Accompanying the experiment and measurement, the identification and elimination of root causes can be effectively improved with numerical modelling, which also grants details to such physical mechanisms that are not even conventionally measurable. This paper is dealing with the following topics from the modelling point of view: an introduction of the different reflow technologies; a brief introduction of primary partial differential equations and calculation procedures; heat transfer mechanisms and thermomechanical stresses; and a brief summary of the results of selected studies. A short overview is also given about soft computing methods applied in reflow process optimisation.

A Novel Packaged Ultra-High Q Silicon MEMS Butterfly Vibratory Gyroscope.

A novel three-dimensional (3D) wafer-level sandwich packaging technology is here applied in the dual mass MEMS butterfly vibratory gyroscope (BFVG) to achieve ultra-high Q factor. A GIS (glass in silicon) composite substrate with glass as the main body and low-resistance silicon column as the vertical lead is processed by glass reflow technology, which effectively avoids air leakage caused by thermal stress mismatch. Sputter getter material is used on the glass cap to further improve the vacuum degree. The Silicon-On-Insulator (SOI) gyroscope structure is sandwiched between the composite substrate and glass cap to realize vertical electrical interconnection by high-vacuum anodic bonding. The Q factors of drive and sense modes in BFVG measured by the self-developed double closed-loop circuit system are significantly improved to 8.628 times and 2.779 times higher than those of the traditional ceramic shell package. The experimental results of the processed gyroscope also demonstrate a high resolution of 0.1°/s, the scale factor of 1.302 mV/(°/s), and nonlinearity of 558 ppm in the full-scale range of ±1800°/s. By calculating the Allen variance, we obtained the angular random walk (ARW) of 1.281°/√h and low bias instability (BI) of 9.789°/h. The process error makes the actual drive and sense frequency of the gyroscope deviate by 8.989% and 5.367% compared with the simulation.

Advanced Packaging Solution to Hermetically Packaging Microelectronic Devices

Hermetic sealing microelectronic devices in package become more and more of a challenge for manufacturers due to the complexity of thermal management, getter integration, and material selection and interactions. Such complexity drives the original equipment manufacturer (OEM) to deliver the equipment and technology to meet manufacturers' requirements. This study has successfully demonstrated that a vacuum reflow technology is able to deliver packages with an excellent hermetic seal. The measured leak rates of these two package types are about two orders of magnitude better than the requirement by Mil-Std 883 method 1014 specification. The result is clear that optimization of the force applied to the lid and package during seal process is essential and the force density of 5 kPa is able to produce a great hermeticity for the two packages under study. A good solder joint strength is essential to deliver a package with hermeticity but is not enough, while a weak joint strength is not possible to achieve hermeticity.

Shrinking Package Footprint by Embedding Top-Side Real Estate Using Core-to-Core Joining

The electronics industry trend continues to be to continually increase capability and performance within an existing or smaller footprint. Shoehorning all of the required components onto the exterior surface of the PCB has become an increasingly difficult puzzle. The use of stacked microvias instead of plated through holes and stacked ICs in various configurations has freed up some real estate. The use of ever smaller passive devices also saves space, but reintroduces old issues such as tombstoning. The ideal solution would be to provide ‘surface’ real estate within the architecture of the circuit board – like moving items from a desk to a bookshelf – by embedding components into the board. In this paper, an alternative strategy is presented for embedded components. Sub-PCB constructions are built and populated on both sides, and then are joined using an interposer with sintering conductive paste interconnects. Sintering paste z-axis interconnections have been successfully used in this type of core-to-core joining for many years. The combination of the sintering paste interconnect and an interposer element is the key to enabling this architecture. This manufacturing strategy presents a number of advantages. The board may be broken down into logical substructures such as high density, core or RF portions. Each of the sub-PCBs can be fabricated according to best manufacturing practices for that portion of the circuit board rather than trying to fabricate a single complicated board. Yield losses from sequential process steps and multiple laminations may be reduced. The embedded components may be assembled onto the sub-PCBs using conventional solder reflow technology. The component placement can facilitate point-of-source architecture for high electrical performance. The process flow and some laboratory demonstrations of this technique will be presented in this paper.

Mobility based 3D simulation of selective, viscoelastic polymer reflow using surface evolver

This work demonstrates implementation of the main effects of viscoelastic thermal polymer reflow in an efficient energy and mobility based simulation. The concept is based on a finite-element, soap-film method using the free software surface evolver. Properties of a homogeneous 3D volume are thereby represented by a corresponding 2D surface. The simulation only requires the contact angle between polymer and substrate for infinite long reflow times, obtained from fingerprint experiments, and a mobility value as input. The mobility value is a measure for the polymer-chain mobility and is directly linked to the polymer viscosity. This concept allows for an accurate and fast treatment of the thermomechanically complex polymer behavior close to the glass transition. The simulation time scale is linearly related to the experimental time scale allowing for accelerated-time simulations. Simulation and experiment showed a very good agreement. As a generalized concept, the approach presented here can be used for fast and full 3D shape computation during any complex, energy driven geometry optimization process like polymer reflow, viscoelastic wetting or dewetting and droplet coagulation. This simulation may facilitate a faster uptake of grayscale reflow technologies for industrial processes. Supplementary material supports a quick grasp of the simulation approach.

Laser Reflow Technology on High-Q Toroidal Microcavity

Optical microcavities confine light to small model volumes and have ultrahigh quality factor (Q), especially microtoroid cavities, having very broad application prospects. In this paper, we use MEMS (Microelectromechanical System) skills, such as lithography, dry etching to fabricated silica optical microdisks. And after that, a novel processing method based on CO2laser reflow technology is introduced to create microtoroid cavities. The processing details are discussed including light path, laser power and other important parameters. The quality factor of the planar microtoroid cavity was measured by taper-fiber coupling and the average value reach 4.8×105.

Study of a Low Cost Reballing of BGA Method with Lead-Free Solder Paste

Due to environmental consciousness and legislative regulations, lead-free solders have been replaced most of the conventional lead-containing solders in microelectronic industry. In response to the concern over Pb used in electronic products and manufacturing electronics, much work is ongoing to find new parameters for re-balling process. This paper describes a low cost reballing method with lead free solder paste on BGA (Ball Grid Array) packages. It was used a lead free solder paste with composition Sn 96,5%, Ag 3,0% and Cu 0,5% and the reflow technology. The results obtained were compared with the conventional reballing method. The solder properties such as wetting characteristics as well as the amount of solder paste deposited by dispenser onto the substrate bond pads influenced on the formation of the bumps. By controlling the volume of solder paste deposited and the parameters used during the reflow step it was possible to obtain bumps liked semi spherical format that can be used to replace the solder balls on the conventional rework of BGA.

Reliability testing of WLCSP lead-free solder joints

The interfacial reactions of solder joints between Sn-4Ag-0.5Cu solder ball and a couple of presoldered pastes (Sn-7Zn-Al(30ppm) and Sn-3Ag-0.5Cu) were investigated in wafer-level chip-scale package (WLCSP). After appropriate surface mount technology reflow processes on printed circuit boards with a Cu/OSP (organic solderability preservative) surface finish, samples were subjected to 150°C high-temperature storage (HTS) for 1,000 h of aging or 1,000 cycles of a thermal cycling test (TCT). Sequentially, cross-section analysis is scrutinized by scanning electron microscopy/energy dispersive spectrometry and energy probe microanalysis to observe metallurgical evolution in the interface and solder buck itself. It was found that the degradation of the joint shear strength after TCT is more pronounced than that of the shear strength after HTS. Fracture surface analyses of the shear tests show that the degradation of the joint strength for HTS is solely due to the influence of the interfacial IMC grain growth, while the shear strength degradation for TCT is mainly due to the coefficient thermal expansion mismatch from the thermal cycling at the chip-solder interface and can lead to the occurrence of the crack.

Application oriented complex polymer microoptics

Three technologies for precise microoptical elements with more than one optical function and fabricated on wafer-scale are described. The combination of reflow technology and direct laser beam writing results in hybrid microoptical elements, comprising, e.g. refractive and diffractive elements. Another method, selective uv-replication enables for hybrid integration of microoptical elements and optoelectronic wafers and is demonstrated for microlenses integrated on VCSEL and LED-chips. As the third method, double-sided uv-replicated microoptics used, e.g. for micro-telescopes, is demonstrated.

Optimizing the reflow profile via defect mechanism analysis

A reflow profile is proposed which is engineered to optimize soldering performance based on defect mechanism analysis. In general, a slow ramp‐up rate is desired in order to minimize hot slump, bridging, tombstoning, skewing, wicking, opens, solder beading, solder balling, and components cracking. A minimized soaking zone reduces voiding, poor wetting, solder balling, and opens. Use of a low peak temperature lessens charring, delamination, intermetallics, leaching, dewetting, and voiding. A rapid cooling rate helps to reduce grain size as well as intermetallic growth, charring, leaching and dewetting. However, a slow cooling rate reduces solder or pad detachment. The optimized profile favors that the temperature ramps up slowly until reaching about 180°C. Implementation of the optimized profile requires the support of a heating‐efficient reflow technology with a controllable heating rate. Emergence of the forced air convection reflow provides a controllable heating rate. In addition, it is not sensitive to variation in parts’ features, thus allows the realization of the optimized profile.

A decision support system for the Alternative Assembly and Reflow Technology process

The Alternative Assembly and Reflow Technology (AART) process allows for the concurrent reflow soldering of through hole and surface mount components on to a Printed Circuit Board (PCB) assembly. The implementation of the AART process will preclude the need for wave and/or manual soldering. Prior to the implementation of the AART process, the engineer is required to compute the volume of solder paste that is needed to form a robust solder joint. The hole fill that can be anticipated should then be determined. Finally, the stencil apertures need to be designed. The decision support systems developed in this research, and described in this paper, can assist a process engineer with solder volume estimation, hole fill prediction, and with stencil aperture design.

SOLDER PASTE TESTS FOR THE 'AART' PROCESS

The electronics manufacturing arena continuously seeks faster and cheaper methods of assembly of electronic components on the Printed Circuit Board (PCB). This scenario has led to the development of the Alternative Assembly and Reflow Technology (AART) process. AART integrates the assembly of through hole and surface mount components. The mass reflow of the through hole and surface mount components results in considerable cost benefits due to the elimination of wave soldering process. The AART process requires the deposition of a large volume of solder paste at the through hole sites. The solder volume requirements at the through hole sites are satisfied by depositing solder paste into the Plated Through Holes (PTHs) and on the solder mask around the holes. Due to the significance of solder paste in the AART process, it is necessary to evaluate the solder pastes before their use. This research proposed two solder paste tests that will be required to assess solder pastes for the AART process. The modified slump test is aimed at studying the slump behavior of solder paste deposits at through hole sites. The second test, the pullback test, is designed to study the flow of solder paste into the PTHs upon reflow. Eight solder pastes were studied for their applicability to the AART process. Through this study, it was inferred that the slump and the pullback behavior of solder pastes are dependent on each other. Solder pastes tended to perform well during pullback if they have not undergone slumping during the pre-reflow stage.

A Study of Solder Paste Rheology for The Alternative Assembly and Reflow Technology (AART) Process

ABSTRACTSolder paste performance related properties such as stencil print quality, viscosity, thixotropy, and slump resistance are of great importance in the pre-reflow stages of the electronics assembly process. This paper focuses on the study of the rheological behavior of solder paste and its correlation to process performance during the various steps of the Alternative Assembly and Reflow Technology (AART) process. This technology aims to integrate the Printed Circuit board (PCB) assembly process for both through hole and surface mount components. Four solder pastes were considered in this study and their rheological characteristics were identified through flow and oscillation tests. The oscillation tests provided the linear viscoelastic characteristics of solder paste whereas the flow tests revealed information on the yield stress as well as the degree of shear-thinning and thixotropy of the solder paste. Pastes with high elastic properties and yield stress exhibited good hot slump resistance. Furthermore, extensive shear thinning of the paste facilitated the filling of the Plated-Through-Hole (PTH) sites. Recommendations are provided for tailoring the properties of a solder paste to meet the needs of the AART process.

Aluminum Reflow Sputtering

The scaling of integrated-circuit device dimensions in the horizontal direction has caused an increase in aspect ratios of contact holes and vias without a corresponding scaledown in vertical dimensions. Conventional sputtering has become unreliable for handling higher aspect-ratio via/contact holes because of its poor step coverage. Several studies have attempted to overcome this problem by using W-CVD and reflow technology. The W-CVD is used for practical device fabrications. However, this technique has several problems such as poor adhesion to SiO2, poor W surface morphology, greater resistivity than Al, and the need of an etch-back process.Al reflow technology using a conventional DC magnetron sputtering system can simplify device-fabrication processes and achieve high reliability without Al/W interfaces. In particular, the Al reflow technology is profitable for multi-level interconnections in combination with a damascene process by using Al chemical mechanical polishing (CMP). These interconnections are necessary for miniaturized and high-speed devices because they provide lower resistivity than W and simplify fabrication processes, resulting in lower cost.This article describes recent Al reflow sputtering technologies as well as application of via and interconnect metallization.

New challenges in solder-paste printing

Journal of Electronics ManufacturingVol. 01, No. 01, pp. 29-40 (1991) PapersNo AccessNew challenges in solder-paste printingN.N. EKERE and E.K. LON.N. EKEREDepartment of Aeronautical and Mechanical Engineering, University of Salford, Salford M5 4WT, UK Search for more papers by this author and E.K. LODepartment of Aeronautical and Mechanical Engineering, University of Salford, Salford M5 4WT, UK Search for more papers by this author https://doi.org/10.1142/S0960313191000059Cited by:14 PreviousNext AboutSectionsPDF/EPUB ToolsAdd to favoritesDownload CitationsTrack CitationsRecommend to Library ShareShare onFacebookTwitterLinked InRedditEmail AbstractThe stencil printing of solder paste for the reflow soldering of surface-mounted components is at present an art. Although the process is known to be governed by complex interactions between large numbers of variables, and empirical data have been accumulated to define their interrelationships, there is a lack of fundamental knowledge of the process and, consequently, inadequate understanding of printing capabilities. The increasing availability and use of fine-pitch components in surface-mount applications have shown the need for more accurate solder-paste prints. Recent developments in fine-particle pastes, water-soluble and no-clean pastes have also introduced additional requirements for printing. To meet these and other new challenges promptly and effectively, process models representing stencil printing are required to explain the effects of key operational parameters and process variables. They, together with other empirical data, will provide the basis for formulating fundamental and equipment-independent rules for solder-paste printing. This paper examines up-to-date industrial challenges in solder-paste printing. It outlines the urgent need to control the printing process better, reviews new developments in solder-paste formulation, printer design and printing methods, and describes existing analytical models developed to represent the off-contact screen printing of ink in thick-film technology. The applicability of these models to solder-paste stencil printing is discussed. The paper concludes with the suggestion of studying the mechanisms of solder-paste printing. The results of the study will provide a tool kit designed to enable the surface-mount industry to maximize the flexibility of its production equipment in handling a wide range of products.Keywords:Surface mount technologysolder-paste printingfine pitch components FiguresReferencesRelatedDetailsCited By 14Analysis of solder mask roughness and stencil shape influence on void formation in solder jointsMartin Kozak, Petr Vesely and Karel Dusek3 March 2023 | Welding in the World, Vol. 60Particle Level Modelling of Solder Pastes Rheological Behaviour in Viscosity MeasurementTareq Al-Ma'aiteh and Oliver Krammer1 May 2019A new coating technology on solder powders to improve solderabilityChen-Yi Chen, Ruei-Ying Sheng and Hsiang-Chuan Chen1 Oct 2017A study of SnAgCu solder paste transfer efficiency and effects of optimal reflow profile on solder depositsE.H. Amalu, W.K. Lau, N.N. Ekere, R.S. Bhatti and S. Mallik et al.1 Jul 2011 | Microelectronic Engineering, Vol. 88, No. 7Evaluation of rheological properties of lead-free solder pastes and their relationship with transfer efficiency during stencil printing processE.H. Amalu, N.N. Ekere and S. Mallik1 Jun 2011 | Materials & Design, Vol. 32, No. 6Fine pitch stencil printing using enclosed printing systemsLing Chunxian Zou, Milos Dusek, Martin Wickham and Christopher Hunt1 Apr 2003 | Soldering & Surface Mount Technology, Vol. 15, No. 1Using computer models to identify optimal conditions for flip‐chip assembly and reliabilityChristopher Bailey, Hua Lu, Greg Glinski, Daniel Wheeler and Phil Hamilton et al.1 Mar 2002 | Circuit World, Vol. 28, No. 1Very fast transmission line pulsing of integrated structures and the charged device modelHorst Gieser and Markus Haunschild1 Oct 1998 | IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part C, Vol. 21, No. 4A Study of Solder Paste Rheology for The Alternative Assembly and Reflow Technology (AART) ProcessS.T. Murthy, D. Manessis, K. Srihari and G.R. Westby10 February 2011 | MRS Proceedings, Vol. 515Solder Paste Dispensing in Robotic SMD ReworkN. Geren and N.N. Ekere1 Jan 1994 | Soldering & Surface Mount Technology, Vol. 6, No. 1Making Circuits More than Once: The Manufacturing Challenges of Electronics Intensive ProductsD J Williams, P P Conway and D C Whalley9 August 2016 | Proceedings of the Institution of Mechanical Engineers, Part B: Journal of Engineering Manufacture, Vol. 207, No. 2Experimental Study of the Printing of Solder Paste Using the Metal Blade Squeegee SystemI. Ismail, S. H. Mannan, N. N. Ekere and E. K. Lo1 Jan 1993Simulation of the stencil printing process [solder pastes]G.P. Glinski, C. Bailey and K. PericleousThe study of the response of solder pastes under sinusoidal vibrationD. He, N.N. Ekere and M.A. Currie Recommended Vol. 01, No. 01 Metrics History Received 1 May 1991 Accepted 1 June 1991 KeywordsSurface mount technologysolder-paste printingfine pitch componentsPDF download

The Feasibility of Ultrasonically Bonding Surface Mount Components to Printed Circuit Boards

The potentially highly automated process of surface mounting electronic components directly onto a substrate or printed circuit board possesses a very weak link. Component movement subsequent to placement and before or during solder reflow leads to defect conditions such as tombstoning or rotational misalignment. This work investigates the feasibility of replacing this ‘weak’ assembly step(s) with ultrasonics. The selection and modification of suitable ultrasonic equipment is described as in the bonding of chip components onto PCBs. Reliability analysis of the resultant bonds along with bond quality in terms of shear strength and appearance under scanning electron microscope and optical microscope is studied. The results show that, with certain preferred directions of ultrasonic weld, weld preload and weld time bond strengths obtained compare very favourably with those achieved with the present surface mount technology reflow process, hence establishing the feasibility of ultrasonics for this application.

Hybrid IC structures using solder reflow technology: Tsuneaki Kamei, Masanori Makamura, Hisashi Ariyoshi and Masanobu Doken IEEE Trans. Components, Hybrids, Mfg Technol. Chmt-2, (2) 208 (June 1979)

Hybrid IC structures using solder reflow technology: Tsuneaki Kamei, Masanori Makamura, Hisashi Ariyoshi and Masanobu Doken IEEE Trans. Components, Hybrids, Mfg Technol. Chmt-2, (2) 208 (June 1979)

Hybrid IC structures using solder reflow technology: T. Kamel, N. Nakamura, H. Ariyoshi and M. Doken Proc. IEEE 28th Electron. Components Conf., Anaheim, 24–26 April 1978, p.172

Hybrid IC structures using solder reflow technology: T. Kamel, N. Nakamura, H. Ariyoshi and M. Doken Proc. IEEE 28th Electron. Components Conf., Anaheim, 24–26 April 1978, p.172

Hybrid IC structures using solder reflow technology : T. Kamei, M. Nakamura, H. Ariyoshi and M. Doken. Proc. IEEE 28th Electron. Components Conf., Anaheim, 24–26 April 1978, p. 172

Hybrid IC structures using solder reflow technology : T. Kamei, M. Nakamura, H. Ariyoshi and M. Doken. Proc. IEEE 28th Electron. Components Conf., Anaheim, 24–26 April 1978, p. 172