Reed-Solomon Codec Research Articles

PAM-4 based long-range free-space-optics communication system with self injection locked QD-LD and RS codec

A secure four-level pulse amplitude modulation (PAM-4) based free-space-optics (FSO) communication system with self-injection-locked quantum dash-laser diode (QD-LD) and Reed–Solomon (RS) encoding scheme is proposed and demonstrated. This system transmit 88 Gbps data over 555-m long optical free-space link, with the help of eight modes of a self injection-locked QD-LD. Self-injection-locking technique diminishes the cost of master laser diode for external injection-locking. The RS coding technique keeps the signal safe from the external noise and decrease the power penalty. The clear eye-diagram and good bit error rate (BER) value established the feasibility of the system.

Real-Time Video Transmission of Visible Light Communication Based on LED

In order to realize the video image transmission and the excellent lighting function of the visible light communication system, a LED-based visible light communication method and system is proposed. Based on the field programmable gate array (FPGA) hardware, the RS channel coding is applied to the visible light communication system. A pulse position decision algorithm is proposed, which is applied to the receiver of the visible light communication system to meet the error-free decision of the signal. The design of the system is based on the analog-to-digital conversion circuit, which provides a large signal dynamic range for the pulse position decision algorithm, and designs the LED driver based on the bias circuit to realize the fast broadband modulation of the signal. The test results show that the combined application of pulse position decision algorithm and Reed-Solomon codec can reduce the error of system signal and meet the real-time and reliable transmission of signal. The system can display the received video in real time from the receiver, and the whole system communication distance up to 5 m.

FPGA based area efficient RS(23, 17) codec

Generally in digital communication systems and storage mediums, Reed---Solomon (RS) codes are employed to detect and correct errors. RS code is a promising code for Ultra Wide Band (UWB) which is ideally suitable for wireless application. Design of compact, high-speed and low-power RS(23, 17) code is challenging for today's wireless communication systems. Here, an optimization algorithm is introduced which is very simple and it is employed to reduce the number of XOR gates required to design constant Galois Field (GF) multipliers. In this paper, a compact RS(23, 17) encoder and decoder circuit is designed and implemented for Ultra Wide Band(UWB) application. The number of two input XOR gates is reduced by 29.27 (20.00) and 56.10 (66.15) % respectively for local and global optimization compared to unoptimized RS encoder (syndrome block) without increasing its delay. The proposed algorithm is also employed to design the RS(204, 188) and RS(255, 223) encoder. All designs are simulated and synthesized for Vertex4 FPGA platform. Proposed algorithm is also used for the design of Chien Search and Forney blocks. Implemented RS(23, 17) codec requires lesser number of slices and LUTs over the unoptimized RS codec. The synthesis results reflect that the proposed design is suitable for resource constraint applications.

Evaluation of software based redundancy algorithms for the EOS storage system at CERN

EOS is a new disk based storage system used in production at CERN since autumn 2011. It is implemented using the plug-in architecture of the XRootD software framework and allows remote file access via XRootD protocol or POSIX-like file access via FUSE mounting. EOS was designed to fulfill specific requirements of disk storage scalability and IO scheduling performance for LHC analysis use cases. This is achieved by following a strategy of decoupling disk and tape storage as individual storage systems. A key point of the EOS design is to provide high availability and redundancy of files via a software implementation which uses disk-only storage systems without hardware RAID arrays. All this is aimed at reducing the overall cost of the system and also simplifying the operational procedures.This paper presents the advantages and disadvantages of redundancy by hardware (most classical storage installations) in comparison to redundancy by software. The latter is implemented in the EOS system and achieves its goal by spawning data and parity stripes via remote file access over nodes. The gain in redundancy and reliability comes with a trade-off in the following areas:• Increased complexity of the network connectivity• CPU intensive parity computations during file creation and recovery• Performance loss through remote disk couplingAn evaluation and performance figures of several redundancy algorithms are presented for dual parity RAID and Reed-Solomon codecs. Moreover, the characteristics and applicability of these algorithms are discussed in the context of reliable data storage systems.

Application in DSP/FPGA Design of Matlab/Simulink

As an off-line simulation tool, the modular modelling method of Matlab/Simulik has the features of high efficiency and visualization. In order to realize the fast design and the simulation of prototype systems, the new method of SignalWAVe/Simulink mix modelling is presented, and the Reed-Solomon codec encoder-decoder model is built. Reed-Solomon codec encoder-decoder model is simulated by Simulink. Farther, the C language program and model the .out executable file are created by SignalWAVe RTW Options module, which completes the hard ware co-simulation. The simulation result conforms to the theoretical analysis, thus it has proven the validity and the feasibility of this method.

GENERIC REED SOLOMON ENCODER

Normal 0 false false false IN X-NONE X-NONE MicrosoftInternetExplorer4 Reed Solomon (RS) codes is a mechanism to detect and correct burst of errors in data transmission and storage systems. It provides a solid introduction to foundation mathematical concept of Galois Field algebra and its application. With the development of digital hardware technology, the RS concepts were brought into reality, i.e. the implementation of RS codec chips. This paper presents the development steps of a generic RS encoder using VHDL. The encoder is able to handle generic width of data, variable length of information, number of error as well as variable form of primitive polynomial and generator polynomial used in the system. The design has been implemented for FPGA chip Xilinx XC3S200-5FT256 and has a better performance than commercially available equivalent encoder. Keywords: reed solomon, error correction codes, galois field, VHDL

The software implementation of decoding for RS code based on a new degree computationless modified Euclid (DCME) algorithm

PurposeThe purpose of this paper is to design a decoding software for the Reed‐Solomon (RS) codes, which are using an efficient degree computationless algorithm based on the Euclidean algorithm. As a consequence, the complexity of this new decoding algorithm is dramatically reduced.Design/methodology/approachApplying the rules of polynomial in finite field, operation modules which can carry out multiplication, inverse calculation in GF(28) are designed with “C++” language, and a RS codec software based on these is implemented. In this software, the new decoding algorithm computes the error locator polynomial and the error evaluator polynomial simultaneously without performing polynomial divisions, and there is no need for the degree computation cell and the degree comparison cell.FindingsOwing to the help of this software, the paper can easily perform the RS code for different values of t and different primitive polynomials over GF(2m) without re‐designing the programme.Originality/valueIt will be served as an efficient auxiliary technique for algorithm development and verification together with hardware design and debugging. Furthermore, an illustrative example of (255, 223) RS code using this program shows that the speed of the decoding process is approximately three times faster than that of the conventional decoding software.

Systolic and Non-Systolic Scalable Modular Designs of Finite Field Multipliers for Reed–Solomon Codec

In this paper, we present efficient algorithms for modular reduction to derive novel systolic and non-systolic architectures for polynomial basis finite field multipliers over GF(2m) to be used in Reed-Solomon (RS) codec. Using the proposed algorithm for unit degree reduction and optimization of implementation of the logic functions in the processing elements (PEs), we have derived an efficient bit-parallel systolic design for finite field multiplier which involves nearly two-thirds of the area-complexity of the existing design having the same time-complexity. The proposed modular reduction algorithms are also used to derive efficient non-systolic serial/parallel designs of field multipliers over GF(28) with different digit-sizes, where the critical path and the hardware-complexity are further reduced by optimizing the implementation of modular reduction operations and finite field accumulations. The proposed bit-serial design involves nearly 55% of the minimum of area, and half the minimum of area-time complexity of the existing bit-serial designs. Similarly, the proposed digit-serial/parallel designs involve significantly less area, and less area-time complexities compared with the existing designs of the same digit-size. By parallel modular reduction through multiple degrees followed by appropriate logic-level sub-expression sharing; a hardware-efficient regular and modular form of a balanced-tree bit-parallel non-systolic multiplier is also derived. The proposed bit-parallel non-systolic pipelined design involves less than 65% of the area and nearly two-thirds of the area-time complexity of the existing bit-parallel design for a RS codec, while the non-pipelined form offers nearly 25% saving of area with less time-complexity.

Analysis of Errors and Erasures in Parity Sharing RS Codecs

Reed Solomon (RS) codes are widely used to protect information from errors in transmission and storage systems. Most of the RS codes are based on GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> ) Galois Fields and use a byte to encode a symbol providing codewords up to 255 symbols. Codewords with more than 255 symbols can be obtained by using GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) Galois fields with m > 8, but this choice increases the complexity of the encoding and decoding algorithms. This limitation can be superseded by introducing parity sharing (PS) RS codes that are characterized by a greater flexibility in terms of design parameters. Consequently, a designer can choose between different PS code implementations in order to meet requirements such as bit error rate (BER), hardware complexity, speed, and throughput. This paper analyzes the performance of PS codes in terms of BER with respect to the code parameters, taking into account either random error or erasure rates as two independent probabilities. This approach provides an evaluation that is independent of the communication channel characteristics and extends the results to memory systems in which permanent faults and transient faults can be modeled, respectively, as erasures and random errors. The paper also provides hardware implementations of the PS encoder and decoder and discusses their performances in terms of hardware complexity, speed, and throughput.

A Low Complexity Design of Reed Solomon Code Algorithm for Advanced RAID System

This paper presents a new low complexity design of Reed Solomon model, which is the key technology for RAID system advanced codec. The real-time constraint of codec leads to a heavy computational bottleneck on today's data storage devices. To overcome this problem, design analysis and optimization of Reed Solomon code are addressed at the algorithmic level. First, the dominant calculation of spreading function is replaced with small look- , up tables. Second, a method which greatly reduces the number of multipliers in performing the multiplication operations of the codec process is proposed to reduce the RAID (Redundant Array of Inexpensive Disks) system codec complexity while maintaining the quality. Moreover, our algorithm can be expanded to correct multiple failed disks. Therefore, the failed data in disks can be recovered and system still can work as usual without broken. This technique is different from the traditional methods. The proposed design could be implemented in a real-time Reed Solomon codec RAID system with reduction of hardware complexity by 28%. A hybrid strategy considering both data layout and load of storage nodes has a 13-25% higher I/O performance than conventional RS RAID.

The front-end SOC for a Blu-ray disc recorder

This article introduces issues on the implementation of a front-end processor for Blu-ray disc (BD) recorder applications. This processor includes partial response maximum likelihood, a data processor block, and servo blocks. The nonlinear equalizer is designed to boost high-frequency signal components without increasing intersymbol interference. It can improve the quality of the high-frequency signal fed into the Viterbi detector, reduce jitter, and offer more tilt margins to the system. Due to the proposed nonlinear equalizer in PRML, less than 2 /spl times/ 10/sup -4/ of the symbol error rate (SER), defined as the BD format book, is achieved with the tangential tilt margin of /spl plusmn/0.5/spl deg/. This system on a chip carries DP functions of a parity preserve/prohibit repeat minimum transition runlength (RMTR) (17PP) modem, Reed-Solomon (RS) codec, and buffer management. The Teaklite DSP is embedded for control functions such as focus servo, track servo, and auto calibration. It contains 12 million transistors in a 50 mm/sup 2/ die, and is fabricated in 0.18 /spl mu/m 1-poly 5-metal (1P5M) CMOS technology.

Design of Application-Specific Instructions and Hardware Accelerator for Reed-Solomon Codecs

This paper presents new application-specific digital signal processor (ASDSP) instructions and their hardware accelerator to efficiently implement Reed-Solomon (RS) encoding and decoding, which is one of the most widely used forward error control (FEC) algorithms. The proposed ASDSP architecture can implement various programmable primitive polynomials, and thus, hardwired RS codecs can be replaced. The new instructions and their hardware accelerator perform Galois field (GF) operations using the proposed GF multiplier and adder. Therefore, the proposed digital signal processor (DSP) architecture can significantly reduce the number of clock cycles compared with existing DSP chips. The proposed GF multiplier was implemented using the Faraday 0.25m standard cell library and it can perform RS decoding at a rate up to 228.1 Mbps at 130 MHz.

Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs

Reed-Solomon (RS) coders are used for error-control coding in many applications such as digital audio, digital TV, software radio, CD players, and wireless and satellite communications. Traditionally, RS coders have been implemented using dedicated hardware. This paper considers software-based implementation of RS codecs. A hardware-software codesign approach is used to design the finite field datapath in a domain-specific digital signal processor (DSP) with low-energy RS codecs application in mind. These datapaths are designed to accommodate programmability with respect to the primitive polynomial as well as the field degree m. A novel heterogeneous digit-serial approach is proposed, where the heterogeneity corresponds to the use of different digit sizes in the multiply-accumulate (MAC) and degree reduction (DEGRED) subarrays. The salient feature of this digit-serial approach is that only the digit cells are implemented in hardware and the finite field multiplications are performed digit-serially in software by dynamically scheduling the internal digit-level operations. Efficient scheduling strategies for digit-serial finite field multiplications are presented and applied to the design of low-energy high-performance RS codecs in software. Significant energy and energy-latency reductions can be achieved using the digit-serial datapaths, as compared with the traditional approach where a combined MAC-DEGRED (parallel multiplier) unit is used. It is concluded that for two-error-correcting RS(n, k) codes over finite field GF(2/sup 8/), datapath containing a parallel MAC unit (of digit size eight) and a DEGRED unit with digit size two (or four) leads to RS codecs with the least energy consumption and energy-latency products; with these datapath architectures and appropriate digit-serial scheduling strategies, more than 60% energy reduction and more than one-third energy-latency reduction can be achieved compared with the parallel multiplication datapath-based approach.

Faster ADSL modem structure with increased correcting capabilities

A faster structure for an asynchronous digital subscriber line (ADSL) modem is presented. The simulation results show an improvement of up to 50%, depending on the application. The structure exploits the path remaining idle in single latency transmission, through the Reed Solomon codecs, improving the correcting capabilities without increasing the latency.

Design automation of Reed-Solomon codecs using VHDL

This paper describes the development of a VHDL core for generating Reed-Solomon codecs. The parameters of the required Reed-Solomon code are entered into the VHDL core as constants (generics) and the resulting description can then be synthesized to any appropriate technology. Codecs generated using the core have been shown to be hardware efficient, with design times a fraction of those required for handcrafted designs and the core can therefore be used by any non-specialist to generate Reed-Solomon codecs for any application.

Finite field division based on recursive division algorithm and composite fields

A new division scheme for GF(2m) is presented This scheme is based on the recursive division algorithm and composite fields ofthe form GF(22n) (m = 2n). The new division scheme offers reduced time complexity ofapproximately O(2n) when compared to traditional bit-serial architectures with O(22n). The scheme also offers lower hardware requirements when compared to bit-parallel architectures. The circuit architecture presented supports implementation in VLSI systems due to its regular and hardware efficient structures and is therefore suited to the implementation of Reed-Solomon codecs.

The design of Reed-Solomon codecs over the, dual basis

In this paper we consider the implementation of Reed-Solomon (RS) codecs. It: is suggested that the most appropriate basis for RS codecs to operate over is the dual basis. The bit-serial Berlekamp multiplier has long been known to be suitable for implementation in RS encoders, but here we also consider its use in RS decoders. The Berlekamp multiplier was previously thought suitable only for use in constant multipliers because it operates over both the dual basis and the polynomial basis. However, work on establishing optimal dual bases to the polynomial basis allows for the design of fist and hardware-efficient 2-variable input dual basis multipliers which can be utilized in RS decoders. Accordingly, we quantify the advantages of utilizing these dual basis multipliers throughout RS codecs. These multipliers have also been utilized in the design of two codecs, a (15, 11) RS codec and a (31, 9) RS codec.

Decoding double-error-correcting Reed-Solomon codes

The decoding of double-error-correcting (DEC) Reed-Solomon (RS) codes is considered. It is shown that by modifying a well known decoding algorithm for DEC RS codes and solving the error-locator polynomial by Berlekamp's method for solving quadratic equations, efficient hardware architectures can be derived. Furthermore, these architectures are particularly suited to implementation over the dual basis. As an example, the architecture of a (15, 11) RS codec is described. The approaches discussed here also lend themselves to the decoding of double-error-correcting/triple-error-detecting RS codes and allow for reduced decoding times compared with alternative approaches to decoding these codes.

Reed-Solomon VLSI codec for advanced television

A VLSI implementation of a Reed-Solomon codec circuit is reported. The 1.6- mu m double metal CMOS chip is 8.2 mm by 8.4 mm, contains 200000 transistors, operates at a sustained data rate of 80 Mbits/s and executes up to 1000 MOPS while consuming less than 500 mW of power. The 10-MHz sustained byte rate for the data is independent of the error pattern. The circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths of 255 bytes as well as shortened codes are supported with no external buffering. Erasure corrections as well as random error corrections are supported with selectable correction of up to ten symbol errors. Corrected data is output at a fixed latency. These features make this Reed-Solomon processor suitable for use in advanced television systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design of Reed-Solomon (16,12) codec for North American Advanced Train Control System

The design of the codec for the ATCS radio data link is considered. The code is defined. The encoding algorithm, the decoding algorithm, and Galois field arithmetic are discussed. Implementation of the Reed-Solomon codec as a stand-alone system in order to provide a possibility of real-time bit-rate measurement is discussed. The implementation of this codec using three different 8-b and 16-b microprocessors/microcomputers is described. Their complexity and throughput are discussed. >