Abstract
This paper presents new application-specific digital signal processor (ASDSP) instructions and their hardware accelerator to efficiently implement Reed-Solomon (RS) encoding and decoding, which is one of the most widely used forward error control (FEC) algorithms. The proposed ASDSP architecture can implement various programmable primitive polynomials, and thus, hardwired RS codecs can be replaced. The new instructions and their hardware accelerator perform Galois field (GF) operations using the proposed GF multiplier and adder. Therefore, the proposed digital signal processor (DSP) architecture can significantly reduce the number of clock cycles compared with existing DSP chips. The proposed GF multiplier was implemented using the Faraday 0.25m standard cell library and it can perform RS decoding at a rate up to 228.1 Mbps at 130 MHz.
Highlights
With the rapid progress of communication technologies, various broadband access systems have been developed, such as very-high-data-rate digital subscriber line (VDSL) cable modem and wireless LAN, gigabit Ethernet, 4G wireless communication, and so forth
The software defined radio (SDR) can support various communication standards since a common hardware platform can be adapted for various communication standards by means of software [1]
This paper presents new application-specific digital signal processor (DSP) (ASDSP) instructions and their hardware accelerator to efficiently implement RS codecs
Summary
With the rapid progress of communication technologies, various broadband access systems have been developed, such as very-high-data-rate digital subscriber line (VDSL) cable modem and wireless LAN, gigabit Ethernet, 4G wireless communication, and so forth. ASIC chips face several limitations such as lack of flexibility for various communication standards, high development costs, and slow time-to-market. Due to these restrictions, implementation methods have been changed to digital signal processor (DSP)-based communication systems that can have advantages in several aspects [2]. This paper presents new application-specific DSP (ASDSP) instructions and their hardware accelerator to efficiently implement RS codecs. Having application-specific instructions and their hardware accelerator for the RS algorithm, ASDSP can support various broadband communication standards.
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