FPGA based area efficient RS(23, 17) codec

Abstract

Generally in digital communication systems and storage mediums, Reed---Solomon (RS) codes are employed to detect and correct errors. RS code is a promising code for Ultra Wide Band (UWB) which is ideally suitable for wireless application. Design of compact, high-speed and low-power RS(23, 17) code is challenging for today's wireless communication systems. Here, an optimization algorithm is introduced which is very simple and it is employed to reduce the number of XOR gates required to design constant Galois Field (GF) multipliers. In this paper, a compact RS(23, 17) encoder and decoder circuit is designed and implemented for Ultra Wide Band(UWB) application. The number of two input XOR gates is reduced by 29.27 (20.00) and 56.10 (66.15) % respectively for local and global optimization compared to unoptimized RS encoder (syndrome block) without increasing its delay. The proposed algorithm is also employed to design the RS(204, 188) and RS(255, 223) encoder. All designs are simulated and synthesized for Vertex4 FPGA platform. Proposed algorithm is also used for the design of Chien Search and Forney blocks. Implemented RS(23, 17) codec requires lesser number of slices and LUTs over the unoptimized RS codec. The synthesis results reflect that the proposed design is suitable for resource constraint applications.