Abstract
A VLSI implementation of a Reed-Solomon codec circuit is reported. The 1.6- mu m double metal CMOS chip is 8.2 mm by 8.4 mm, contains 200000 transistors, operates at a sustained data rate of 80 Mbits/s and executes up to 1000 MOPS while consuming less than 500 mW of power. The 10-MHz sustained byte rate for the data is independent of the error pattern. The circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths of 255 bytes as well as shortened codes are supported with no external buffering. Erasure corrections as well as random error corrections are supported with selectable correction of up to ten symbol errors. Corrected data is output at a fixed latency. These features make this Reed-Solomon processor suitable for use in advanced television systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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