Abstract
This paper describes the development of a VHDL core for generating Reed-Solomon codecs. The parameters of the required Reed-Solomon code are entered into the VHDL core as constants (generics) and the resulting description can then be synthesized to any appropriate technology. Codecs generated using the core have been shown to be hardware efficient, with design times a fraction of those required for handcrafted designs and the core can therefore be used by any non-specialist to generate Reed-Solomon codecs for any application.
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