Abstract
This paper describes the development of a VHDL core for generating Reed-Solomon codecs. The parameters of the required Reed-Solomon code are entered into the VHDL core as constants (generics) and the resulting description can then be synthesized to any appropriate technology. Codecs generated using the core have been shown to be hardware efficient, with design times a fraction of those required for handcrafted designs and the core can therefore be used by any non-specialist to generate Reed-Solomon codecs for any application.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.