Reduced Interface State Research Articles

Analysis of photodiode and barrier properties of CoPc/n-Ge heterojunction under various illumination wavelengths

The present investigation reports the analysis of barrier parameters of the CoPc/n-Ge heterojunction photodiode under varied illumination wavelengths from 500 nm to 1200 nm in steps of 25 nm. The efficiency of this photodiode was also summarized using responsivity, detectivity and quantum efficiency for different illumination wavelengths. The photocurrent seems to be maximum for 850 nm and 1175 nm and shows higher responsivity of 1.72 A/W and 2.38 A/W at 775 nm and 1125 nm wavelength respectively. The quantum efficiency of the photodiode was found to be 275 % at illumination wavelength of 775 nm and 263 % at 1125 nm. For the selective illumination wavelengths (775 nm, 850 nm, 1125 nm and 1175 nm), the electrical properties of the CoPc/n-Ge photodiode were studied. Noticeable variation in the barrier parameters of the photodiode is observed with illumination than compared to dark. Significantly, the series resistance was found to be decreased and shunt resistance is increased with illumination wavelength than compared to dark. Current conduction mechanisms were also investigated in both the forward and reverse bias of the photodiode. The forward current transport processes show that at moderately high bias the current conduction might be associated with TCLC. It is also evidenced from the reverse conduction mechanism that at low reverse voltages PFE is found to be dominant whereas SE is dominant at high reverse voltages. The reduced interface state densities at the CoPc/n-Ge interface were observed under illumination than compared to dark.

A 1T'-MoTe2/GaN van der Waals Schottky junction for self-powered UV imaging and optical communication.

Schottky-type self-powered UV photodetectors are promising for next-generation imaging systems. Nevertheless, conventional device fabrication using high-energy metal deposition brings unintentional interface defects, leading to deteriorated device performance and inhomogeneities. Emerging two-dimensional (2D) metallic materials offer an alternative pathway to overcoming such limitations because of their naturally passivated surfaces and the ease of combining with mature bulk semiconductors via van der Waals (vdW) integration. Here, we report the controllable preparation of MoTe2 in the pure 1T' phase and the fabrication of a high-performance 1T'-MoTe2/GaN vdW Schottky photodiode. With the reduced interface states and suppressed dark current as low as 20 pA at zero bias, the photodiode exhibits a remarkable UV-to-visible (R350/R400) rejection ratio of 1.6 × 104, a stable photoresponsivity of ∼50 mA W-1 and a detectivity of 3.5 × 1012 Jones under 360 nm illumination. The photocurrent ON/OFF ratio reaches ∼4.9 × 106 under 10.5 mW irradiation (360 nm). In particular, the 1T'-MoTe2/GaN Schottky diode shows excellent weak-light detection capability, which could detect a 3 nW 360 nm laser and the light emission from a lighter with a pronounced Ilight/Idark ratio of ∼2. Finally, the applications of the device in self-powered UV imaging and optical communication are demonstrated. These results reveal the great prospects of 2D/3D integration in multifunctional optoelectronics, which may inspire novel 2D-related devices and expand their applications in widespread fields.

Carrier Recombination Dynamics of Surface-Passivated Epitaxial (100)Ge, (110)Ge, and (111)Ge Layers by Atomic Layer Deposited Al2O3

Germanium (Ge) and its heterostructures with compound semiconductors offer a unique optoelectronic functionality due to its pseudo-bandgap nature, that can be transformed to a direct bandgap material by providing strain and/or mixing with tin. Moreover, two crystal surfaces, (100)Ge and (110)Ge, that are technologically important for ultralow power fin or nanosheet transistors, could offer unprecedented properties with reduced surface defects after passivating these surfaces by atomic layer deposited (ALD) dielectrics. In this work, the crystallographically oriented epitaxial Ge/AlAs heterostructures were grown and passivated with ALD Al2O3 dielectrics, and the microwave photoconductive decay (μ-PCD) technique was employed to evaluate carrier lifetimes at room temperature. The X-ray photoelectron spectroscopy analysis reveals no role of orientation effect in the quality of the ALD Al2O3 dielectric on oriented Ge layers. The carrier lifetimes measured using the μ-PCD technique were benchmarked against unpassivated Ge/AlAs heterostructures. Excitation wavelengths of 1500 and 1800 nm with an estimated injection level of ∼1013 cm–3 were selected to measure the orientation-specific carrier lifetimes. The carrier lifetime was increased from 390 ns to 565 ns for (100)Ge and from 260 ns to 440 ns for (110)Ge orientations with passivation, whereas the carrier lifetime is almost unchanged for (111)Ge after passivation. This behavior indicates a strong dependence of the measured lifetime on surface orientation and surface passivation. The observed increase (>1.5×) in lifetime with Al2O3-passivated (100)Ge and (110)Ge surfaces is due to the lower surface recombination velocity compared to unpassivated Ge/AlAs heterostructures. The enhancement of carrier lifetime from passivated Ge/AlAs heterostructures with (100)Ge and (110)Ge surface orientations offers a path for the development of nanoscale transistors due to the reduced interface state density.

Horizontal Arrays of One-Dimensional van der Waals Heterostructures as Transistor Channels

The nanotube/dielectric interface plays an essential role in achieving superb switching characteristics of carbon nanotube-based transistors for energy-efficient computation. Formation of van der Waals heterostructures with hexagonal boron nitride nanotubes could be an effective means to reduce interface state density, but the need for isolating nanotubes during the formation of coaxial outer layers has hindered the fabrication of their horizontal arrays. Here, we develop a strategy to create isolated heterostructure arrays using aligned carbon nanotubes grown on a quartz substrate as starting materials. Air-suspended arrays of carbon nanotubes are prepared by a dry transfer technique and then used as templates for the coaxial wrapping of boron nitride nanotubes. We then fabricate the transistors, where boron nitride serves as interfacial layers between carbon nanotube channels and conventional gate dielectrics, showing hysteresis-free characteristics owing to the improved interfaces. We have also gained a deeper understanding of the strain applied on inner carbon nanotubes, as well as the inhomogeneity of the outer coating, by characterizing individual heterostructures over trenches and on a substrate surface. The device fabrication and characterization presented here essentially do not require elaborate electron microscopy, thus paving the way for the practical use of one-dimensional van der Waals heterostructures for nanoelectronics.

Current-voltage (I-V) characteristics of Au/n-Ge heterostructure based on cobalt phthalocyanine (CoPc) interlayer

The influence of cobalt phthalocyanine (CoPc) interlayer on the I-V measurements of Au/n-Ge (pristine) contacts is investigated. I-V characteristics reveals the decrease in the reverse leakage current of CoPc interlayer contacts than compared to contacts without interlayer. The Schottky barrier parameters were described using forward I-V measurements by assuming standard thermionic emission mechanism. The barrier height (BH) of the contact with CoPc interlayer is significantly improved than compared to pristine contact. The observed BHs of pristine and CoPc interlayer contacts are found to be 0.63 eV and 0.67 eV respectively. Reduced interface state density and altered space charges on the n-Ge surface reduces tunneling resistance, may account for the larger BH observed in contacts with CoPc interlayer than pristine contacts. The series resistance evaluated for the contacts using Cheung’s method shows its consistency with Norde method. The observed series resistance value of the Au/CoPc/n-Ge contacts found to be significantly smaller in magnitude than Au/n-Ge contacts. The current conduction mechanism of pristine contact and contact with interlayer was evaluated using double logarithmic I-V plot in the forward bias region. Three regions of conduction mechanisms are observed for Au/CoPc/n-Ge contacts. It is evident that the CoPc interfacial layer considerably changes the conduction mechanism from ohmic conduction to trap charge limited current (TCLC) mechanism at moderately high voltages. The associated transition in the conduction mechanism might be due to the presence of shallow traps (low energy traps) with exponential distribution at the CoPc/n-Ge interface.

Evidence of reduced interface states in Al2O3/AlGaN MIS structures via insertion of ex situ regrown AlGaN layer

We report on the impact of the 3 nm thick ex situ AlGaN regrown layer prior to insulator deposition on the interfacial properties of Al2O3/AlGaN/GaN metal–insulator–semiconductor (MIS) structures. MIS-capacitors (MIScaps) with regrown AlGaN layer exhibited anomalously excessive threshold voltage shift compared to reference sample without regrown AlGaN, suggesting highly reduced interface states density (D it). Moreover, MIScaps with regrown AlGaN layer exhibited “spill-over” in the capacitance–voltage profiles, further evidencing the improved Al2O3/AlGaN interfaces. Fabricated three-terminal MIS-HEMTs with regrown AlGaN showed less hysteresis in transfer curves, enhanced maximum drain current, and increased linearity over the reference device.

Suppression of current dispersion in AlGaN/GaN MISHFETs with in-situ AlN passivation layer

We demonstrate effective reduction of interface states and current collapse in AlGaN/GaN metal insulator semiconductor heterostructure field effect transistor (MISHFETs) with Al2O3 and in-situ AlN passivation layer. Here, first, a 3 nm-thick in-situ AlN layer is grown on AlGaN/GaN structure by using MOCVD at 1070 °C, and second a 7 nm-thick atomic layer deposition (ALD) Al2O3 layer is immediately deposited on the AlN layer. The X-ray photoelectron spectroscopy (XPS) analyses for the Ga 3d core level and multi-frequency capacitance–voltage (C–V) measurement show that the density of interface states originated from the Ga-O bonds, which is dramatically reduced with the in-situ AlN passivation layer. The AlGaN/GaN-based MISHFET with the Al2O3/in-situ AlN layers exhibits the low gate-lag effect (8%), remarkably less than that of the device with the typical GaN capping layer (21.5%). These results indicate that the Al2O3/in-situ AlN double passivation layer is very effective in suppressing the current collapse, and hence, it is found to be the promising method for the fabrication of AlGaN/GaN MISHFETs with enhanced performance.

Interface State Reduction by Plasma-Enhanced Atomic Layer Deposition of Homogeneous Ternary Oxides.

Homogeneous ternary oxides of silicon-, niobium-, and molybdenum-aluminate were deposited by plasma-enhanced ALD using sequential metal precursor pulses prior to the oxidation step, to reduce interfacial defects usually observed in nanolaminate growth. The growth kinetics can be understood in terms of competitive adsorption. Trimethyl aluminum (TMA) is strongly chemisorbed to the growth surface and does not permit coadsorption of any of the other precursors; when we lead with a TMA pulse, the resulting film is always Al2O3. When we lead with the Si or Nb precursors, the growth surface is partially saturated, but open sites are available for TMA coadsorption. The Mo precursor is weakly chemisorbed and is largely displaced by a subsequent TMA dose. As compared to nanolaminate films of the constituent binary oxides, the interface state density is reduced by up to a factor of 5.

Enhanced performances of p-si/n-ZnO self-powered photodetector by interface state modification and pyro-phototronic effect

ZnO based self-powered photodetector (PD) has great application potential in distributing sensor networks and internet of things. However, a large number of surface or interface states within ZnO limit its performance improvement. Here, the surface and interface states of ZnO is greatly eliminated by ultraviolet irradiation as an interfacial modification engineering. Reduction of interface states reduces ohmic resistance, also enhances the tuning role of pyro-phototronic effect. And the transient response currents of the self-powered PD are thus significantly improved with a maximal enhancement factor of more than 5900% for the 325–785 nm broadband stimulating beams. The corresponding response time is decreased to few milliseconds or sub-milliseconds. The results indicate that surface-state reduction of ZnO can effectively enhance the modifying role of pyro-phototronic effect and greatly improve the response performances of the self-powered broadband PDs with great application demands in Internet of things, broad spectral detecting and imaging, and smart optoelectronic devices.

Al(ON) gate dielectrics for 4H-SiC MOS devices

Abstract The gate dielectrics for silicon carbide based MOS devices are still crucial for their performance and reliability. Conventional thermal oxides have a poor interface quality and a low dielectric constant. To mitigate the issues brought about by conventional thermal oxidation, Al(ON) based on atomic layer deposition (ALD) technique is proposed and studied in terms of interface state density and dielectric strength/reliability. To make comparison, the results of AlN and Al2O3 grown using the same ALD technique, are included as well. It is shown that by incorporating of nitrogen/AlN, Al(ON) can reduce interface state density and border trap density. In addition, its dielectric strength/reliability in terms of time-zero-dielectric breakdown (TZDB) also improves.

Alternate lanthanum oxide/silicon oxynitride-based gate stack performance enhancement due to ultrathin oxynitride interfacial layer for CMOS applications

Metal–insulator–semiconductor (MIS)-based Pt/La2O3/SiOXNY/p-Si/Pt structures are fabricated using ultrathin silicon oxynitride (SiOXNY ~ 4 nm) interfacial layer underneath of lanthanum (III) oxide (La2O3 ~ 7.8 nm) with Pt as gate electrode for CMOS applications. Capacitance–voltage (C–V) characteristics of Pt/La2O3/SiOXNY/p-Si/Pt at 500 kHz showed a positive gate bias threshold voltage (Vth) shift of ~ 0.43 V (~ 43.8%) and flat-band (Vfb) shift of ~ 1.24 V (~ 42.3%) as compared to Pt/La2O3/p-Si/Pt MIS structures, attributing to the reduction in effective positive oxide charges at La2O3/SiOXNY/Si gate stack. Likewise, conductance–voltage (G–V) characteristics show ~ 0.56 (~ 44.4%) reduction in FWHM for Pt/La2O3/SiOXNY/p-Si/Pt as compared to Pt/La2O3/p-Si/Pt MIS structures revealing the reduction in interface states at La2O3/SiOXNY/Si interface. There is a considerable reduction of effective oxide charge concentration (Neff) ~ 3.99 × 1010 cm−2 by (~ 15.2%) and ~ 56.8% lower gate leakage current density ~ 4.47 × 10−7 A/cm2 (|J|–V) at − 1 V for SiOXNY based MIS structures w.r.t its counterpart. Capacitance–time (C–t) characteristics, constant voltage stress (CVS) and temperature measurements for C–V and |J|–V demonstrate the considerable retention ~ 12 years, electrical improvement and reliability of MIS structures. The depth profile analysis X-ray photoelectron spectroscopy (XPS) for SiOXNY/Si gate stack clearly reveals that less nitrogen concentration in bulk than SiOXNY/Si interface. Atomic force microscopy (AFM) micrographs of La2O3/Si and SiOXNY/Si showed the significantly lesser r.m.s roughness of ~ 1.11 ± 0.39 nm and ~ 0.97 ± 0.11 nm, respectively. Thus, the ultrathin SiOXNY interfacial layer underneath of La2O3 demonstrates a significantly improved electrical performance and prelude the gate stack strong potential for reliable CMOS logic devices and integrated circuits.

Behavior of SiNx/SiO2 Double Layer for Surface Passivation of Compensated p-Type Czochralski Silicon Wafers

Surface passivation of Czochralski (Cz) p-type compensated silicon using a hydrogenated silicon nitride/silicon oxide (SiNx-H/SiO2) double layer (hereinafter called SiNx/SiO2) has been investigated. The characteristics of the deposited films depended strongly on surface preparation, deposition process, and annealing parameters. Fourier-transform infrared (FTIR) spectroscopy was used to analyze the chemical bonds in the Si–SiNx/SiO2 structure, and quasi-steady-state photoconductance (QSSPC) measurements were used to evaluate the minority-carrier lifetime (τeff), to check the quality of the passivation. The results showed that, after SiNx/SiO2 double-layer deposition, τeff remained rather poor (13.29 μs). This low degree of passivation is principally due to the appearance of an inversion layer after oxidation, inducing switching of the semiconductor type at the surface. This inversion layer is due to the segregation properties of both boron and phosphorus impurities. This phenomenon was highlighted by secondary-ion mass spectrometry (SIMS) characterization, revealing a substantial phosphorus concentration near the Si–SiO2 interface and penetration of boron inside the oxide, with concentration of 1 × 1018 cm−3 and 4 × 1018 cm−3, respectively. Annealing at 400°C under low pressure of 3.34 × 10−3 kPa improved the minority-carrier lifetime to τeff = 15.94 μs, leading to enhanced surface passivation related to the reduced interface state density and improved statistical distribution of different bonding environments.

Plasma enhanced chemical vapor deposition of SiO2 and SiNx on AlGaN: Band offsets and interface studies as a function of Al composition

In this work, the authors characterized the interface of plasma enhanced chemical vapor deposition (PECVD) dielectrics, SiO2 and SiNx with AlGaN as a function of Al composition. SiO2 is found to exhibit type I straddled band alignment with positive conduction and valence band offsets for all Al compositions. However, the interface Fermi level is found to be pinned within the bandgap, indicating a significant density of interface states. Hence, SiO2 is found to be suitable for insulating layers or electrical isolation on AlGaN with breakdown fields between 4.5 and 6.5 MV cm−1, but an additional passivating interlayer between SiO2 and AlGaN is necessary for passivation on Al-rich AlGaN. In contrast, Si-rich PECVD SiNx is found to exhibit type II staggered band alignment with positive conduction band offsets and negative valence band offsets for Al compositions <40% and type I straddled band alignment with negative conduction and valence band offsets for Al compositions >40% and is, hence, found to be unsuitable for insulating layers or electrical isolation on Al-rich AlGaN in general. In contrast to passivating stoichiometric LPCVD Si3N4, no evidence for interface state reduction by depositing SiNx on AlGaN is observed.

Fermi‐level depinning in germanium Schottky junction using nitrogen plasma treatment

Fermi-level depinning in germanium (Ge) through nitrogen (N2) plasma treatment is demonstrated. The Ge surface was exposed to N2 plasma for 1 min without heat treatment, resulting in the formation of 2.5 nm-thick GeO x N y layer with uniform surface and interface morphologies. Ohmic and Schottky behaviours were obtained for Al contacts to N2 plasma-treated n- and p-type Ge with barrier heights of 0.09 and 0.40 eV, respectively. Fermi-level depinning could be attributed to the reduction in interface states caused by the passivation of Ge surface by highly uniform GeO x N y layer.

Oxygen Pressure Controlled Oxidation for Gate Insulator Process of SiC MOSFETs

For the improvement of a SiC/SiO2 interface of SiC-MOSFET, we examined O2 partial pressure (PO2) controlled (OPC) oxidation process for the gate oxide formation. The OPC oxidation process has a potential to reduce interface state density (Dit) at SiC/SiO2 interface by using appropriate PO2 and oxidation temperature. However the process requires rapid thermal annealing which is not suitable for mass production. Thus we investigated the process using furnace. First, we optimized the OPC oxidation process for the furnace to realize low interface defect density. Secondly, we confirmed that reduction of Dit was determined by desorption of excess carbon in OPC process by the C–ψs measurement and X-ray photoelectron spectroscopy. Finally, a DMOSFET was fabricated using optimized OPC process. We measured the transfer characteristics, and found that the drain current with OPC was larger than without OPC process.

Suppression of short channel effects in FinFETs using crystalline ZrO2 high-K/Al2O3 buffer layer gate stack for low power device applications

The electrical characteristics of FinFETs with a crystalline ZrO2/Al2O3 buffer layer gate stack and a crystalline ZrO2 high-K dielectric single layer, along with different fin widths and gate lengths, are investigated. Compared with the FinFETs with a single layer of crystalline ZrO2 high-K dielectric, the gate stack comprising the crystalline ZrO2/Al2O3 buffer layer on FinFETs leads to the suppression of short channel effects in terms of a low drain induced barrier lowering, reduced threshold voltage roll-off, and improved subthreshold swing. The ON/OFF current ratio and gate leakage current of FinFETs are also improved by the crystalline ZrO2/Al2O3 buffer layer gate stack. The improvement of electrical characteristics is ascribed to the reduced interface state density and gate leakage as a result of the insertion of an Al2O3 buffer layer between ZrO2 and Si. The results demonstrate that the crystalline ZrO2/Al2O3 buffer layer structure is a promising high-K gate stack for next-generation nanoscale transistors.

Structure and Surface Morphology of Thermal SiO<sub>2</sub> Grown on 4H-SiC by Metal-Enhanced Oxidation Using Barium

Surface morphology and electrical properties of silicon dioxide (SiO2) on 4H-SiC substrates formed by metal-enhanced oxidation (MEO) using barium (Ba) atoms were systematically investigated. It was found that severe surface roughening caused by Ba-MEO can be suppressed by using SiO2 capping prior to MEO. The Ba atoms at the SiO2/SiC interface were found to diffuse to the oxide surface through the deposited SiO2 capping layer, and then the Ba density reduced to ~1014 cm-2 before stable MEO. The resulting SiO2/SiC interface showed the reduced interface state density but the insulating property of the oxides was significantly degraded.

Insight into metal-enhanced oxidation using barium on 4H-SiC surfaces

Metal-enhanced oxidation (MEO) using ultrathin Ba layers on 4H-SiC surfaces was investigated by physical and electrical characterizations. We found that while comparable oxidation rates were enhanced for Si- and C-face surfaces even at a low temperature, significant surface and interface roughness were induced by initial MEO termed the incubation period. Depth profiling revealed that although most Ba atoms aggregated on the oxide surface, a tiny amount (∼1014 cm−2) remaining at the oxide interface was responsible for the following stable MEO reaction and the reduced interface state density with the drawbacks of degraded leakage current and breakdown characteristics of SiC-MOS devices.

Reduction of interface states by hydrogen treatment at the aluminum oxide/4H-SiC Si-face interface

Processes to form aluminum oxide as a gate insulator on the 4H-SiC Si-face are investigated to eliminate the interface state density (DIT) and improve the mobility. Processes that do not involve the insertion or formation of SiO2 at the interface are preferential to eliminate traps that may be present in SiO2. Aluminum oxide was formed by atomic layer deposition with hydrogen plasma pretreatment followed by annealing in forming gas. Hydrogen treatment was effective to reduce DIT at the interface of aluminum oxide and SiC without a SiO2 interlayer. Optimization of the process conditions resulted in DIT for the metal oxide semiconductor (MOS) capacitor of 1.7×1012 cm−2eV−1 at 0.2 eV, and the peak field-effect mobility of the MOS field-effect transistor (MOSFET) was approximately 57 cm2V−1s−1.

Effect of nitrogen incorporation into Al-based gate insulators in AlON/AlGaN/GaN metal–oxide–semiconductor structures

The superior physical and electrical properties of aluminum oxynitride (AlON) gate dielectrics on AlGaN/GaN substrates in terms of thermal stability, reliability, and interface quality were demonstrated by direct AlON deposition and subsequent annealing. Nitrogen incorporation into alumina was proven to be beneficial both for suppressing intermixing at the insulator/AlGaN interface and reducing the number of electrical defects in Al2O3 films. Consequently, we achieved high-quality AlON/AlGaN/GaN metal–oxide–semiconductor capacitors with improved stability against charge injection and a reduced interface state density as low as 1.2 × 1011 cm−2 eV−1. The impact of nitrogen incorporation into the insulator will be discussed on the basis of experimental findings.