Reduction Of Interface State Density Research Articles

Carrier Recombination Dynamics of Surface-Passivated Epitaxial (100)Ge, (110)Ge, and (111)Ge Layers by Atomic Layer Deposited Al2O3

Germanium (Ge) and its heterostructures with compound semiconductors offer a unique optoelectronic functionality due to its pseudo-bandgap nature, that can be transformed to a direct bandgap material by providing strain and/or mixing with tin. Moreover, two crystal surfaces, (100)Ge and (110)Ge, that are technologically important for ultralow power fin or nanosheet transistors, could offer unprecedented properties with reduced surface defects after passivating these surfaces by atomic layer deposited (ALD) dielectrics. In this work, the crystallographically oriented epitaxial Ge/AlAs heterostructures were grown and passivated with ALD Al2O3 dielectrics, and the microwave photoconductive decay (μ-PCD) technique was employed to evaluate carrier lifetimes at room temperature. The X-ray photoelectron spectroscopy analysis reveals no role of orientation effect in the quality of the ALD Al2O3 dielectric on oriented Ge layers. The carrier lifetimes measured using the μ-PCD technique were benchmarked against unpassivated Ge/AlAs heterostructures. Excitation wavelengths of 1500 and 1800 nm with an estimated injection level of ∼1013 cm–3 were selected to measure the orientation-specific carrier lifetimes. The carrier lifetime was increased from 390 ns to 565 ns for (100)Ge and from 260 ns to 440 ns for (110)Ge orientations with passivation, whereas the carrier lifetime is almost unchanged for (111)Ge after passivation. This behavior indicates a strong dependence of the measured lifetime on surface orientation and surface passivation. The observed increase (>1.5×) in lifetime with Al2O3-passivated (100)Ge and (110)Ge surfaces is due to the lower surface recombination velocity compared to unpassivated Ge/AlAs heterostructures. The enhancement of carrier lifetime from passivated Ge/AlAs heterostructures with (100)Ge and (110)Ge surface orientations offers a path for the development of nanoscale transistors due to the reduced interface state density.

Horizontal Arrays of One-Dimensional van der Waals Heterostructures as Transistor Channels

The nanotube/dielectric interface plays an essential role in achieving superb switching characteristics of carbon nanotube-based transistors for energy-efficient computation. Formation of van der Waals heterostructures with hexagonal boron nitride nanotubes could be an effective means to reduce interface state density, but the need for isolating nanotubes during the formation of coaxial outer layers has hindered the fabrication of their horizontal arrays. Here, we develop a strategy to create isolated heterostructure arrays using aligned carbon nanotubes grown on a quartz substrate as starting materials. Air-suspended arrays of carbon nanotubes are prepared by a dry transfer technique and then used as templates for the coaxial wrapping of boron nitride nanotubes. We then fabricate the transistors, where boron nitride serves as interfacial layers between carbon nanotube channels and conventional gate dielectrics, showing hysteresis-free characteristics owing to the improved interfaces. We have also gained a deeper understanding of the strain applied on inner carbon nanotubes, as well as the inhomogeneity of the outer coating, by characterizing individual heterostructures over trenches and on a substrate surface. The device fabrication and characterization presented here essentially do not require elaborate electron microscopy, thus paving the way for the practical use of one-dimensional van der Waals heterostructures for nanoelectronics.

Current-voltage (I-V) characteristics of Au/n-Ge heterostructure based on cobalt phthalocyanine (CoPc) interlayer

The influence of cobalt phthalocyanine (CoPc) interlayer on the I-V measurements of Au/n-Ge (pristine) contacts is investigated. I-V characteristics reveals the decrease in the reverse leakage current of CoPc interlayer contacts than compared to contacts without interlayer. The Schottky barrier parameters were described using forward I-V measurements by assuming standard thermionic emission mechanism. The barrier height (BH) of the contact with CoPc interlayer is significantly improved than compared to pristine contact. The observed BHs of pristine and CoPc interlayer contacts are found to be 0.63 eV and 0.67 eV respectively. Reduced interface state density and altered space charges on the n-Ge surface reduces tunneling resistance, may account for the larger BH observed in contacts with CoPc interlayer than pristine contacts. The series resistance evaluated for the contacts using Cheung’s method shows its consistency with Norde method. The observed series resistance value of the Au/CoPc/n-Ge contacts found to be significantly smaller in magnitude than Au/n-Ge contacts. The current conduction mechanism of pristine contact and contact with interlayer was evaluated using double logarithmic I-V plot in the forward bias region. Three regions of conduction mechanisms are observed for Au/CoPc/n-Ge contacts. It is evident that the CoPc interfacial layer considerably changes the conduction mechanism from ohmic conduction to trap charge limited current (TCLC) mechanism at moderately high voltages. The associated transition in the conduction mechanism might be due to the presence of shallow traps (low energy traps) with exponential distribution at the CoPc/n-Ge interface.

Demonstration of AlGaN/GaN MISHEMT on Si with Low-Temperature Epitaxy Grown AlN Dielectric Gate

AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMT) with a low-temperature epitaxy (LTE)-grown single crystalline AlN gate dielectric were demonstrated for the first time and the post-gate annealing effects at 400 °C were studied. The as-deposited LTE-AlN MISHEMT showed a maximum drain current (IDmax) of 708 mA/mm at a gate bias of 4 V and a maximum extrinsic transconductance (gmmax) of 129 mS/mm. The 400 °C annealed MISHEMT exhibited an increase of 15% in gmmax, an order of magnitude reduction in reverse gate leakage and about a 3% suppression of drain current (ID) collapse. The increase of gmmax by post-gate annealing is consistent with the increase of 2DEG mobility. The suppression of ID collapse and the reduction of gate leakage current is attributed to the reduction of interface state density (5.0 × 1011 cm−2eV−1) between the AlN/GaN interface after post-gate annealing at 400 °C. This study demonstrates that LTE grown AlN is a promising alternate material as gate dielectric for GaN-based MISHEMT application.

Reduction of interface state density in coaxial TiO2/Ge nanowire assembly-based heterostructure and superior photodetection

This paper compares the advantages of a catalyst-free vertically aligned coaxial titanium dioxide nanowire/germanium nanowire (TiO2-NW/Ge-NW) heterostructure compared to basic germanium nanowire (Ge-NW) on silicon (Si) substrate. Both were fabricated using the glancing angle deposition (GLAD) technique integrated into an electron beam evaporation system. The study is focussed on the successful suppression of native germanium oxide (GeO2) as well as the reduction of interface state density (Dit) by incorporating TiO2-NW. X-ray diffraction (XRD) patterns confirm the successful growth of rutile phase TiO2-NW in the coaxial TiO2-NW/Ge-NW assembly at room temperature. The crystal size analysis was carried out using the Scherrer equation and it confirmed the decrease in crystal size of GeO2 in the coaxial TiO2-NW/Ge-NW assembly. FEGSEM reveals the growth of vertically oriented NWs. Capacitance and conduction voltage data were used to extract the interface state density (Dit). The presence of TiO2 reduced the interface defect in the TiO2-NW/Ge-NW heterostructure compared to the bare Ge-NW sample. The optical absorption study showed that TiO2-NW/Ge-NW samples exhibited enhancement in the UV region primarily due to the presence of TiO2. The electrical characterization of Ag/TiO2-NW/Ge-NW/Si and Ag/Ge-NW/Si revealed a low dark current of −1.056 × 10−7 A/cm2 for Ag/TiO2-NW/Ge-NW/Si compared to −8.39 × 10−7 A/cm2 for Ag/Ge-NW/Si. Ag/TiO2-NW/Ge-NW/Si exhibited a superior rectification ratio, increased detectivity, and enhanced noise equivalent power compared to the Ag/Ge-NW/Si device. The TiO2-NW/Ge-NW heterostructure exhibited a fast temporal response with rise and fall times of ∼0.047 s and ∼0.037 s, respectively.

Consideration on SiO2/4H-SiC Band Alignment Modulation by NO Annealing

Post oxidation annealing (POA) process in NO ambient is one of the standard techniques to control 4H-SiC MOS characteristics, which introduces nitrogen atoms to the surface of SiC by substituting the topmost carbon atoms [1]. Together with the reduction of interface state density, however, a significant negative shift of threshold voltage is often caused by this process [2]. In this study, we clarified that such negative shift is not only caused by fixed charge introduction but originates from an anomalous modulation of band alignment of SiO2/4H-SiC interface.First we systematically studied the flat-band voltage (VFB) of SiO2/4H-SiC (0001) n-type MOS capacitors with various oxide thickness, fabricated by conventional dry oxidation followed by the POA in NO/N2 = 1/2 ambient at 1150°C. From the oxide thickness dependence of the VFB we can deduce the expected value of VFB when the effects of fixed charges are removed. As a result we found an anomalous negative shift of VFB irrespective of oxide thickness, which was enlarged by extending NO annealing duration [3]. This phenomenon would be explainable by assuming a dipole layer formation at the interface by SiC surface nitridation.Next this phenomenon was investigated from the viewpoint of SiO2/4H-SiC band alignment change by two kinds of analyzing methods: the valence-band spectra analysis using x-ray photoelectron spectroscopy (XPS) and the energy barrier height characterization of Fowler-Nordheim (F-N) currents. By systematic comparisons of the valence-band XPS of SiO2/SiC stack with a few-nm-thick SiO2 and that of SiC substrate without SiO2, we could see a clear trend that the valence-band offset between SiC and SiO2 changes monotonically by the NO-POA durations. Since no change of bandgap of SiO2 was suggested from O1s loss spectrum, this phenomenon was regarded as the band alignment change by the nitridation of SiC surface. To our surprise, this trend appeared in opposite direction for 4H-SiC (0001) and (000-1) stacks: the NO-POA increases the conduction-band offset for a few hundreds of meV in case of 4H-SiC (0001) stack, but it decreases in the case of 4H-SiC (000-1) stack for a similar amount [3]. For the F-N current analysis, the I-V characteristics at -150°C were evaluated where we confirmed the leakage currents were perfectly dominated by F-N tunneling mechanism. We could clearly see the trend of decreasing of F-N tunneling current for 4H-SiC (0001) MOS capacitors by extending NO annealing duration which was attributable to the increase of conduction-band offset, while the opposite trend was observed for 4H-SiC (000-1) MOS capacitors. These trends are quite consistent with the results of XPS analysis. Thus we could conclude that the observed change of VFB shift by NO-POA as described above was determined by the band alignment change at SiO2/4H-SiC interface. A significant difference of the band alignment on (0001) and (000-1) was also clarified which would be the reason for the disagreement of VFB of the capacitors on those crystal faces.Since the nitrogen atoms replacing the topmost carbon atoms on SiC surface are considered to be coordinated by three Si atoms, this replacement may induce an additional polarization at the interface. Considering the fact that high density of nitrogen (~1014 atoms/cm2) are introduced [1] mostly in the top of SiC, a significant magnitude of polarization in the order of hundreds of meV would be achievable. We speculate this array of polarized structure at the SiC surface would be observed as a formation of interface dipole layer. With this model we can clearly explain the reason why 4H-SiC (0001) and (000-1) interfaces showed the dipole layer formation toward different direction by nitrogen introduction, taking account of the opposite Si-N bond arrangements on those interfaces. We consider that this phenomenon is one of the essential reasons to cause unexpected threshold voltage shifts often reported for SiC MOSFETs with NO-POA.[1] J. Rozen et al., J. Appl. Phys. 105, 124506 (2009).[2] G. Chung et al., Appl. Surf. Sci. 184, 399 (2001).[3] T. H. Kil and K. Kita, Appl. Phys. Lett. 116, 122103 (2020).

Al(ON) gate dielectrics for 4H-SiC MOS devices

Abstract The gate dielectrics for silicon carbide based MOS devices are still crucial for their performance and reliability. Conventional thermal oxides have a poor interface quality and a low dielectric constant. To mitigate the issues brought about by conventional thermal oxidation, Al(ON) based on atomic layer deposition (ALD) technique is proposed and studied in terms of interface state density and dielectric strength/reliability. To make comparison, the results of AlN and Al2O3 grown using the same ALD technique, are included as well. It is shown that by incorporating of nitrogen/AlN, Al(ON) can reduce interface state density and border trap density. In addition, its dielectric strength/reliability in terms of time-zero-dielectric breakdown (TZDB) also improves.

The Correlation between the Reduction of Interface State Density at the SiO<sub>2</sub>/SiC Interface and the NO Post-Oxide-Annealing Conditions

We fabricated SiO2/4H-SiC (0001) MOS capacitors with oxidation temperature at 1350°C, followed by post-oxide-annealing (POA) in NO simply by the control of POA temperatures and times. A correlation between the reduction of interface state density and the increasing of N concentration at the interface has been indicated by C-ψs measurement and secondary ion mass spectrometry (SIMS). The SiO2/4H-SiC interface density decreased when POA temperature was elevated, and the sample annealed at 1300°C for 30min showed the lowest interface state density about 1.5×1012 cm-2eV-1 at Ec-E=0.3 eV when the N concentration is 11.5×1020 cm-3. Meanwhile, the SiO2 /4H-SiC interface annealed at 1200°C for 120min showed the highest N concentration at the 4H-SiC/SiO2 interface is 12.5×1020 cm-3, whereas the interface state density is 2.5×1012 cm-2eV-1 at Ec-E=0.3 eV higher than 1300°C for 30min. The results suggested that higher temperature POA might be much more efficiency in decreased the 4H-SiC MOS interface density with increasing the N area concentration.

Behavior of SiNx/SiO2 Double Layer for Surface Passivation of Compensated p-Type Czochralski Silicon Wafers

Surface passivation of Czochralski (Cz) p-type compensated silicon using a hydrogenated silicon nitride/silicon oxide (SiNx-H/SiO2) double layer (hereinafter called SiNx/SiO2) has been investigated. The characteristics of the deposited films depended strongly on surface preparation, deposition process, and annealing parameters. Fourier-transform infrared (FTIR) spectroscopy was used to analyze the chemical bonds in the Si–SiNx/SiO2 structure, and quasi-steady-state photoconductance (QSSPC) measurements were used to evaluate the minority-carrier lifetime (τeff), to check the quality of the passivation. The results showed that, after SiNx/SiO2 double-layer deposition, τeff remained rather poor (13.29 μs). This low degree of passivation is principally due to the appearance of an inversion layer after oxidation, inducing switching of the semiconductor type at the surface. This inversion layer is due to the segregation properties of both boron and phosphorus impurities. This phenomenon was highlighted by secondary-ion mass spectrometry (SIMS) characterization, revealing a substantial phosphorus concentration near the Si–SiO2 interface and penetration of boron inside the oxide, with concentration of 1 × 1018 cm−3 and 4 × 1018 cm−3, respectively. Annealing at 400°C under low pressure of 3.34 × 10−3 kPa improved the minority-carrier lifetime to τeff = 15.94 μs, leading to enhanced surface passivation related to the reduced interface state density and improved statistical distribution of different bonding environments.

Reduction of interface state density in SiC (0001) MOS structures by low-oxygen-partial-pressure annealing

We report that annealing in low-oxygen-partial-pressure (low-pO2) ambient is effective in reducing the interface state density (DIT) at a SiC (0001)/SiO2 interface near the conduction band edge (EC) of SiC. The DIT value at EC − 0.2 eV estimated by a high (1 MHz)-low method is 6.2 × 1012 eV−1 cm−2 in as-oxidized sample, which is reduced to 2.4 × 1012 eV−1 cm−2 by subsequent annealing in O2 (0.001%) at 1500 °C, without interface nitridation. Although annealing in pure Ar induces leakage current in the oxide, low-pO2 annealing does not degrade the oxide dielectric property (breakdown field ∼10.4 MV cm−1).

Improved Threshold Voltage Instability in 4H-SiC MOSFETs with Atomic Layer Deposited SiO<sub>2</sub>

This study reports the electrical characteristics and reliability of the atomic layer deposited SiO2 on the 4H-SiC substrate. By controlling the thickness of SiO2 in each ALD cycle, improved device properties like mobility and gate leakage were obtained as compared to the single deposition. Moreover, the optimized process dramatically reduces the threshold voltage shift under positive and negative bias stresses. This improvement can be attributed to the effective removal of unreacted metal-organic precursors, active traps, and broken bonds in the ALD SiO2 dielectrics as well as reduction in interface state density at SiC/SiO2 interface.

Oxygen Pressure Controlled Oxidation for Gate Insulator Process of SiC MOSFETs

For the improvement of a SiC/SiO2 interface of SiC-MOSFET, we examined O2 partial pressure (PO2) controlled (OPC) oxidation process for the gate oxide formation. The OPC oxidation process has a potential to reduce interface state density (Dit) at SiC/SiO2 interface by using appropriate PO2 and oxidation temperature. However the process requires rapid thermal annealing which is not suitable for mass production. Thus we investigated the process using furnace. First, we optimized the OPC oxidation process for the furnace to realize low interface defect density. Secondly, we confirmed that reduction of Dit was determined by desorption of excess carbon in OPC process by the C–ψs measurement and X-ray photoelectron spectroscopy. Finally, a DMOSFET was fabricated using optimized OPC process. We measured the transfer characteristics, and found that the drain current with OPC was larger than without OPC process.

Effects of annealing gas and drain doping concentration on electrical properties of Ge-source/Si-channel heterojunction tunneling FETs

Improvement in the performance of Ge-source/Si-channel heterojunction tunneling FETs (TFETs) with high on-current/off-current (Ion/Ioff) ratio and steep subthreshold swing (SS) is demonstrated. In this paper, we experimentally examine the effects of gas ambient [N2 and forming gas (4% H2/N2)] and a doping concentration in the drain regions on the electrical characteristics of Ge/Si heterojunction TFETs. The minimum SS (SSmin) of 70.9 mV/dec and the large Ion/Ioff ratio of 1.4 × 107 are realized by postmetallization annealing in forming gas. Also, the steep SSmin and averaged SS (SSavr) values of 64.2 and 78.4 mV/dec, respectively, are obtained in low drain doping concentration. This improvement is attributable to the reduction in interface state density (Dit) in the channel region and to the low leakage current in the drain region.

High thermal stability of abrupt SiO2/GaN interface with low interface state density

The effects of postdeposition annealing (PDA) on the interface properties of a SiO2/GaN structure formed by remote oxygen plasma-enhanced chemical vapor deposition (RP-CVD) were systematically investigated. X-ray photoelectron spectroscopy clarified that PDA in the temperature range from 600 to 800 °C has almost no effects on the chemical bonding features at the SiO2/GaN interface, and that positive charges exist at the interface, the density of which can be reduced by PDA at 800 °C. The capacitance–voltage (C–V) and current density–SiO2 electric field characteristics of the GaN MOS capacitors also confirmed the reduction in interface state density (Dit) and the improvement in the breakdown property of the SiO2 film after PDA at 800 °C. Consequently, a high thermal stability of the SiO2/GaN structure with a low fixed charge density and a low Dit formed by RP-CVD was demonstrated. This is quite informative for realizing highly robust GaN power devices.

Suppression of short channel effects in FinFETs using crystalline ZrO2 high-K/Al2O3 buffer layer gate stack for low power device applications

The electrical characteristics of FinFETs with a crystalline ZrO2/Al2O3 buffer layer gate stack and a crystalline ZrO2 high-K dielectric single layer, along with different fin widths and gate lengths, are investigated. Compared with the FinFETs with a single layer of crystalline ZrO2 high-K dielectric, the gate stack comprising the crystalline ZrO2/Al2O3 buffer layer on FinFETs leads to the suppression of short channel effects in terms of a low drain induced barrier lowering, reduced threshold voltage roll-off, and improved subthreshold swing. The ON/OFF current ratio and gate leakage current of FinFETs are also improved by the crystalline ZrO2/Al2O3 buffer layer gate stack. The improvement of electrical characteristics is ascribed to the reduced interface state density and gate leakage as a result of the insertion of an Al2O3 buffer layer between ZrO2 and Si. The results demonstrate that the crystalline ZrO2/Al2O3 buffer layer structure is a promising high-K gate stack for next-generation nanoscale transistors.

Detailed study of SiOxNy:H/Si interface properties for high quality surface passivation of crystalline silicon

In this work, we present a detailed study on the interface and passivation properties of the hydrogenated silicon oxynitride (SiOxNy:H) on the crystalline silicon (c-Si) and their correlations with the film composition. The SiOxNy:H films were synthesized by plasma enhanced chemical vapor deposition (PECVD) at various N2O flow rates, which results in different film composition, in particular the different H-related bonds, such as SiH and NH bonds. Fourier transform infrared spectroscopy measurements show that the concentration of NH bonds increases with the N2O flows from 0 to 30 sccm, while drops below the detection limit at N2O flows above 30 sccm. This changing trend of NH bonds correlates well with the evolution of carrier lifetime of silicon substrate passivated by SiOxNy:H film, indicating the crucial role of NH bonds in surface passivation. It is inferred that during the film deposition and forming gas anneal (FGA) a considerable amount of hydrogen atoms are liberated from the weak type of NH bonds rather than SiH bonds, and then passivate the dangling bonds at the interface, thus resulting in the significant reduction of interface state density and the improved passivation quality. In detail, the interface state density is reduced from ∼5 × 1012 to ∼2 × 1012 cm−2 eV−1 after the FGA, as derived from the high frequency capacitance-voltage (CV) measurements.

Structure and Surface Morphology of Thermal SiO<sub>2</sub> Grown on 4H-SiC by Metal-Enhanced Oxidation Using Barium

Surface morphology and electrical properties of silicon dioxide (SiO2) on 4H-SiC substrates formed by metal-enhanced oxidation (MEO) using barium (Ba) atoms were systematically investigated. It was found that severe surface roughening caused by Ba-MEO can be suppressed by using SiO2 capping prior to MEO. The Ba atoms at the SiO2/SiC interface were found to diffuse to the oxide surface through the deposited SiO2 capping layer, and then the Ba density reduced to ~1014 cm-2 before stable MEO. The resulting SiO2/SiC interface showed the reduced interface state density but the insulating property of the oxides was significantly degraded.

Reduction of interface state density in SiC (0001) MOS structures by post-oxidation Ar annealing at high temperature

We found that post-oxidation Ar annealing at high temperature is effective in reducing the interface state density (Dit) near the conduction band edge (EC) of SiC (0001) MOS structures. The Dit reduction effect is comparable to that of nitridation process (annealing in nitric oxide (NO)) which has been a standard in SiC MOS technologies, without introducing any foreign atoms into the interface/oxide. The generation of fast interface states, which have been pointed out as a problem of nitridation process, is suppressed in the case of Ar annealing. In the proposed method, the final Dit values are mainly determined by the Ar annealing temperature rather than the initial oxidation temperature. The Dit values are not sensitive to the cooling speed, which means that rapid cooling is not necessary in the proposed method.

Reduction of interface state density at SiO2/InAlN interface by inserting ultrathin Al2O3 and plasma oxide interlayers

SiO2/InAlN interfaces formed by plasma‐enhanced chemical vapor deposition were investigated. X‐ray photoelectron spectroscopy showed that the direct deposition of SiO2 onto an InAlN surface led to the oxidation of the InAlN surface. The interface state density, Dit, was on the order of 1012 cm−2 eV−1 (5 × 1012 cm−2 eV−1 at 0.3 eV from the conduction band edge, Ec), which indicated the possibility of improving the interface properties. Reduction of the interface state density was attempted using an Al2O3 interlayer and a plasma oxide interlayer. The insertion of a 2‐nm‐thick Al2O3 interlayer to prevent surface oxidation by plasma reduced Dit slightly. A marked reduction in Dit to less than 1011 cm−2 eV−1 deeper than 0.3 eV from Ec, however, was achieved by the intentional formation of a 1‐nm‐thick plasma oxide layer, formed by N2O plasma oxidation, as an interlayer between SiO2 and InAlN.

Insight into metal-enhanced oxidation using barium on 4H-SiC surfaces

Metal-enhanced oxidation (MEO) using ultrathin Ba layers on 4H-SiC surfaces was investigated by physical and electrical characterizations. We found that while comparable oxidation rates were enhanced for Si- and C-face surfaces even at a low temperature, significant surface and interface roughness were induced by initial MEO termed the incubation period. Depth profiling revealed that although most Ba atoms aggregated on the oxide surface, a tiny amount (∼1014 cm−2) remaining at the oxide interface was responsible for the following stable MEO reaction and the reduced interface state density with the drawbacks of degraded leakage current and breakdown characteristics of SiC-MOS devices.