Reduction In Power Delay Product Research Articles

Efficient design approaches to model CNTFET-based Ternary Schmitt Trigger circuits

Digital computation using radix three offers the benefit of increased information density with less power consumption due to reduced interconnect complexity. Hence this brief presents two architectures for ternary Schmitt trigger designs that are implemented by combining shifting literals, ternary inverters and decoder equivalents using carbon nanotube technology. In the first proposed design, Schmitt trigger hysteresis curves are realized using shifting literals i.e. successor and predecessor cells. The second proposed design employs ternary inverters and a decoder equivalent of intermediate logic level for the implementation. The experimental analysis involves the simulations that are conducted using HSPICE and the standard Stanford CNTFET model. Simulation results confirm that the proposed ternary Schmitt trigger designs outperform in terms of power consumption and power delay product(PDP), showcasing the power reduction average of 75% and PDP reduction average of 79% respectively in comparison to recent counterparts. Moreover, Monte Carlo simulations are conducted to verify the robust operation of proposed designs and lesser deviations are observed in performance parameters towards process variations.

Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications

Stationary random-access memory (SRAM) undergoes an expansion stage, to repel advanced process variation and support ultra-low power operation. Memories occupy more than 80% of the surface in today’s microdevices, and this trend is expected to continue. Metal oxide semiconductor field effect transistor (MOSFET) face a set of difficulties, that results in higher leakage current (Ileakage) at lower strategy collisions. Fin field effect transistor (FinFET) is a highly effective substitute to complementary metal oxide semiconductor (CMOS) under the 45 nm variant due to advanced stability. Memory cells are significant in the large-scale computation system. SRAM is the most commonly used memory type; SRAMs are thought to utilize more than 60% of the chip area. The proposed SRAM cell is developed with FinFETs at 16 nm knot. Power, delay, power delay product (PDP), Ileakage, and stationary noise margin (SNM) are compared with traditional 6T SRAM cells. The designed cell decreases leakage power, current, and read access time. While comparing 6T SRAM and earlier low power SRAM cells, FinFET-based 10T SRAM provides significant SNM with reduced access time. The proposed 10T SRAM based on FinFET provides an 80.80% PDP reduction in write mode and a 50.65% PDP reduction in read mode compared to MOSEFET models. There is an improvement of 22.20% in terms of SNM and 25.53% in terms of Ileakage.

Fast and Low-Power CMOS and CNFET based Hysteresis Voltage Comparator

This paper presents CMOS and CNFET based hysteresis voltage comparators for low-voltage applications. The proposed CMOS and CNFET hysteresis comparators require merely 1.6 and 0.26 µW of power, respectively, which is less than one tenth of the power dissipated by the other advanced hysteresis comparators designs available in literature. The propagation delay observed in the proposed CMOS and CNFET hysteresis comparators are 162 and 47 ps, respectively, which is almost half the delay exhibited by the other hysteresis comparators. Overall, a 93–99% reduction in Power Delay Product (PDP) can be achieved. Furthermore, the proposed design requires only nine transistors compared to the 11–17 transistor requirement in conventional hysteresis comparators, thus saving up to 47% of chip area.

Modified Dual Mode Transmission Gate Diffusion Input Logic for Improving Energy Efficiency

This paper presents a modified energy-efficient Dual Mode Transmission Gate Diffusion Input (DMTGDI) design and is termed as M-DMTGDI. A contention issue in dynamic mode operation of existing DMTGDI design and DMPL design is identified and illustrated through mathematical formulation and simulations. To resolve this concern, the pre-charge/pre-discharge transistor in existing DMTGDI design is replaced by dual mode inverter in the proposal. The functional verification and performance comparison of NAND, NOR, XOR gates and 1-bit full adder based on proposed M-DMTGDI is carried out using 90 nm BSIM4 model card for bulk CMOS using Symica DE tool. The performance of the circuits is evaluated in terms of power, delay and Power Delay Product (PDP) in both static and dynamic modes. The variation of PDP with the ratio of the time the circuit is designed to run in dynamic mode against static mode is also investigated to analyze the energy efficiency of the M-DMTGDI design. The proposed approach offers maximum PDP reduction of 33.52%, 99.39% and 96.61% for 2-input gates as compared to their footed DML, DMPL and DMTGDI counterparts, respectively. The reduction in PDP is quite significant in 1-bit full adder circuit where the corresponding values are 94.18%, 99.41% and 99.79%, respectively.

High-Speed and Energy-Efficient Carry Look-Ahead Adder

The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison.

Energy-Efficient High-Speed ASIC Implementation of Convolutional Neural Network Using Novel Reduced Critical-Path Design

Convolutional Neural Network (CNN) plays an important role in several machine learning tasks related to speech, image, and video processing applications. The increasing demand for faster processing in real-time applications requires high-speed implementation of CNN. However, in general, CNN involves higher latency due to the computationally intensive behavior of the convolutional layer. While state-of-the-art architecture provides efficient dataflow of the convolutional operations, this paper proposes a hardware-efficient, high-speed convolution block for ASIC implementation of the CNN algorithm. The proposed convolution block is designed using a novel bit-level-multiply-accumulator (BLMAC) with a modified Booth encoder and a Wallace reduction tree. The critical path of the overall architecture is significantly shortened due to the time-optimized implementation of the proposed BLMAC, which is a main component of the convolution process. Critical path analysis and dataflow strategy are also provided to demonstrate the acceleration of the proposed design. The proposed architecture was synthesized using Synopsys Design Compiler to prove its accelerated processing. The ASIC synthesis results of the proposed architecture using a 65nm standard cell library show at least 53% reduction in latency, 52.2% reduction in area-delay product, and 54.2% reduction in power-delay product compared to the state-of-the-art architecture.

Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications

Purpose Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels. Design/methodology/approach The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented. Findings The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%. Originality/value The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.

Design of Multiple Node Upset Tolerant Latch in 32 nm CMOS Technology

<p indent=0mm>With continuous scaling of CMOS technology, single event multi-node upset induced by charge sharing effect has become an important factor affecting chip reliability. This paper proposed a novel multi-node upset (MNU) tolerant latch design: LPMNUHL. Based on DICE latch, where single node upset is resilient, the latch builds a mechanism of triple modular redundancy and uses a voter as output. The proposed latch is tolerant to multi-node upset and votes the correct output logic value. What’s more, there is no high impedance state in the latch and soft errors of the internal nodes can be blocked successfully. The latch can not only tolerance triple node upset completely, but also tolerance 90.30% of quadruple node upset. Due to the use of a high-speed transmission path, the clock-gating technology and a clock-gating voter, the proposed latch is low power. In <sc>32 nm</sc> CMOS technology, extensive SPICE simulation results demonstrate that compared with the previous latches, the proposed latch has an average delay reduction of 40.16%, an average power reduction of 44.96%, an average power delay product reduction of 65.40%, and an area reduction of 34.60%. Moreover, the proposed latch is not sensitive to temperature and voltage variations.

2$$\times $$VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process

Since the CMOS technology moving forward swiftly, digital data exchange between chips fabricated using different generations of technologies becomes a problem when the size of printed circuit board-based systems is critical for mobile or wearable devices. To achieve better performance, smaller size, and power efficiency, a 2 $$\times $$ VDD output buffer featured with process, voltage, and temperature detection and the integration of dual-Vth and standard Vth transistors optimized by W/L sizing is proposed. Slew rate (SR) self-adjustment and power–delay product reduction are also verified by Monte Carlo simulations to achieve at least 27.8% improvement and 37.6% reduction. The prototype of this investigation fabricated by a typical 28-nm CMOS process is measured on silicon to attain at least 7.6% SR improvement.

Approximate radix-8 Booth multiplier for low power and high speed applications

Approximate computing is an emerging circuit design technique which reduce the energy consumption with acceptable degradation in accuracy. Three approximate radix-8 Booth multipliers are proposed in this paper to explore the advantages of approximate computing. These multipliers are designed by using two proposed approximate Booth encoders for the generation of approximate partial products. Approximate partial products are introduced into a few number of least significant columns (AC) of the partial product matrix. The proposed multipliers with 16-bit inputs are simulated using a 45-nm CMOS technology library. For AC = 16, the results indicate that the first proposed multiplier reduces power delay product (PDP) and Area by 33% and 23% respectively as compared to conventional radix-8 Booth multiplier. Moreover, it has a Normalized Mean Error Distance (NMED) of 1.43E-5. The second proposed multiplier shows 43% and 31% reduction in PDP and Area respectively with an NMED of 1.664E-5. Similarly, the third proposed multiplier shows 37% and 25% reduction in PDP and Area respectively with an NMED of 1.512E-5. The accuracy of proposed multipliers are verified with real-time applications in image processing and deep learning.

Logically Optimal Novel 4:2 Compressor Architectures for High-Performance Applications

Multipliers are principal arithmetic components that play a key role in determining the performance of DSP architectures. While the efficiency of multipliers relies on optimal reduction of partial products within constraint power-delay values, this can be achieved by ‘compressors’ a precisely designed special arithmetic module. In this manuscript, authors propose low-power high-performance 4:2 compressor architectures. The presented designs perform better than the contemporary designs in terms of latency, improved power-delay and area-delay product values. The principal objective of this work is to design and develop a fast 4:2 compressor circuitry with optimal trade-off between power and area by pristine logical decomposition. All the referenced and proposed designs are simulated and synthesized in synopsys design compiler using prelayout CMOS standard cell library of TSMC 65 nm. From the synthesis results, it can be seen that the proposed model provides 12.5–29.17% reduction in area and 7–14.23% reduction in propagation delay with respect to state-of-the-art 4:2 compressor designs. In addition, to estimate the performance stability in realistic applications, 4-bit, 8-bit and 16-bit Dadda multiplier integrated with proposed compressor cells is implemented and verified. The obtained synthesis results substantiate that Dadda multiplier integrated with proposed compressor cells performs better than conventional and state-of-the-art 4:2 compressor-based variants with 4–8% reduction in propagation delay, upto 23.370% reduction in area-delay product and upto 25.62% reduction in power-delay product for 4-bit multiplication, while 6.77–16.85% reduction in propagation delay, 2.62–18.70% reduction in area-delay product and 15.30–23.20% reduction in power-delay product are achieved for 8-bit multiplication. For 16-bit multiplication it shows upto 47.05% reduction in propagation delay, upto 21.68% reduction in area-delay product and upto 24.42% reduction in power-delay product for 16-bit multiplication.

High-Performance CML approximate full adders for image processing application of laplace transform

PurposeThe high demand for fast, energy-efficient, compact computational blocks in digital electronics has led the researchers to use approximate computing in applications where inaccuracy of outputs is tolerable. The purpose of this paper is to present two ultra-high-speed current-mode approximate full adders (FA) by using carbon nanotube field-effect transistors.Design/methodology/approachInstead of using threshold detectors, which are common elements in current-mode logic, diodes are used to stabilize voltage. Zener diodes and ultra-low-power diodes are used within the first and second proposed designs, respectively. This innovation eliminates threshold detectors from critical path and makes it shorter. Then, the new adders are employed in the image processing application of Laplace filter, which detects edges in an image.FindingsSimulation results demonstrate very high-speed operation for the first and second proposed designs, which are, respectively, 44.7 per cent and 21.6 per cent faster than the next high-speed adder cell. In addition, they make a reasonable compromise between power-delay product (PDP) and other important evaluating factors in the context of approximate computing. They have very few transistors and very low total error distance. In addition, they do not propagate error to higher bit positions by generating output carry correctly. According to the investigations, up to four inexact FA can be used in the Laplace filter computations without a significant image quality loss. The employment of the first and second proposed designs results in 42.4 per cent and 32.2 per cent PDP reduction compared to when no approximate FA are used in an 8-bit ripple adder.Originality/valueTwo new current-mode inexact FA are presented. They use diodes as voltage regulators to design current-mode approximate full-adders with very short critical path for the first time.

Hardware Optimized and Error Reduced Approximate Adder

This paper presents a new hardware optimized and error reduced approximate adder (HOERAA), which is suitable for field programmable gate array (FPGA)- and application specific integrated circuit (ASIC)-based implementations. In this work, we consider a FPGA-based implementation using Xilinx Vivado 2018.3, targeting an Artix-7 FPGA. The ASIC-based realizations are based on a 32/28nm complementary metal oxide semiconductor (CMOS) process. Based on FPGA implementations, we note the following: (i) For 32-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 22% fewer look-up tables (LUTs) and 18.6% fewer registers while reducing the minimum clock period by 7.1% and reducing the power-delay product (PDP) by 14.7%, compared to the native accurate FPGA adder, and (ii) for 64-bit addition involving a 8-bit least significant inaccurate sub-adder, HOERAA requires 11% fewer LUTs and 9.3% fewer registers while reducing the minimum clock period by 8.3% and reducing the PDP by 9.3%, compared to the native accurate FPGA adder. Based on ASIC-style implementations, HOERAA is found to achieve the following reductions in design metrics compared to an optimum accurate carry-lookahead adder: (i) A 15.7% reduction in critical path delay, a 21.4% reduction in area, and a 35% reduction in PDP for 32-bit addition involving a 8-bit least significant inaccurate sub-adder, and (ii) a 15.3% reduction in critical path delay, a 10.7% reduction in area, and a 20% reduction in PDP for 64-bit addition involving a 8-bit least significant inaccurate sub-adder. Moreover, comparisons with other approximate adders show that HOERAA has a significantly reduced average error, mean average error, and root mean square error, while reporting near optimum design metrics.

A Single-Ended 28-nm CMOS 6T SRAM Design with Read-assist Path and PDP Reduction Circuitry

A single-ended six-transistor (6T) SRAM cell composed of a five-transistor (5T) cell and a read-assist low-[Formula: see text] PMOS as foot switch to prevent leakage damaging the data state is proposed in this work. Besides, a power–delay product (PDP) reduction circuitry design for nanoscale SRAMs is also proposed. The proposed PDP reduction circuitry design is composed of an adaptive voltage detection (AVD) circuit generating a boost-enable signal if the process variation is over a predefined range and a half-period word-line boosting (HWB) circuit responding to the enable signal. The proposed SRAM is implemented using TSMC 28-nm CMOS logic technology. PDP reduction is verified to be 41.73% according to the measurement results. The energy per access is 0.0206 pJ given the 800-mV power supply and 40-MHz system clock rate.

A closed-loop ASIC design approach based on logical effort theory and artificial neural networks

Standard cell library is the backbone of modern day application specific integrated circuit (ASIC) design flow provided by electronic design automation (EDA) vendors worldwide. In these libraries, standard cells are generally available in terms of discrete drive strengths with higher drive strength indicating a faster version of the cell belonging to some predefined logic functionality. However, this leads to increased values of area and power consumption in comparison to a lower drive strength standard cell which has slower response time indicating the underlying tradeoff between speed, area and power. A standard cell with discrete drive strength is not always required during the process of logic synthesis and non-availability of standard cells with fractional drive strengths in the aforementioned libraries hugely impacts the overall performance of resulting digital integrated circuits (ICs) and systems [1]. In this paper, a novel technique has been introduced for on-demand generation and inclusion of standard cells in the logic synthesis process leading to availability of a continuous spectrum of standard cells in terms of drive strengths which ultimately provides a platform for closed-loop ASIC design flow. Logical effort (LE) theory has been utilized alongside artificial neural networks (ANNs) in order to implement the proposed methodology. Extensive circuit simulations have been performed using HSPICE in 130 nm/1.2 V CMOS process technology. Preliminary results are encouraging with up to 41.7% and 62.8% reduction in power-delay product (PDP) and power-delay-area product (PDAP) for a 5-stage gate level test circuit. An 8-bit counter realized using the proposed methodology shows up to 29.77% reduction in power dissipation and 37.8% savings in area at varying capacitive loads when compared to conventional logic synthesis technique which employs a library comprising of standard cells with discrete drive strengths. It is noteworthy that the proposed approach is a general technique which can be easily mapped to high complexity circuits and advanced technology nodes. To support this fact, simulation results have also been provided at 90 nm/1 V CMOS process node for the 5-stage test circuit.

Ultralow Power Nonvolatile Logic Based on Spin-Orbit and Exchange Coupled Nanowires

The rapid growth of Internet of Things and emphasis on low power mobile devices has inspired researchers to explore newer devices, such as nonvolatile logic devices. Due to their miniaturized dimensions and zero leakage, spintronic devices are among the most promising devices in literature. In this paper, we propose a new logic style based on spin-orbit and exchange coupled nanowires. Our logic style takes advantage of two key features, namely, spin-orbit coupling and exchange coupling fields to enhance energy efficiency. Furthermore, we demonstrate dedicated input and output paths for the proposed device resulting in inherent asymmetry and simplified operation. Furthermore, thanks to our device structure, fringing dipole fields between devices are eliminated leading to improved area utilization and smaller area. In order to evaluate our proposed logic style, a simulation framework was developed. This simulation framework consists of a micromagnetic dynamics module, electron transport module, and a circuit integrator. Using our simulation framework, we demonstrate 88% reduction in power delay product and 93% reduction in the delay and 37% reduction in the area for an inverter compared to previously logic styles based on motion of domain walls.

LDPC check node implementation using reversible logic

Reversible logic is an emerging digital design paradigm which promises low energy dissipation; thanks to its information-lossless nature. True potential of this exciting concept can only be assessed by facing the design of practical complexity applications. Low density parity check (LDPC) decoding is one such application from forward error correction domain. The core of LDPC decoding is the check node (CN) processor, which executes the decoding algorithm and constitutes a major portion of decoder's overall power consumption. This work proposes a low-power LDPC CN architecture using reversible logic gates. Transistor level design and full custom layout of proposed architecture is carried out on UMC 90 nm complementary metal–oxide–semiconductor technology. All reversible blocks of proposed CN are optimised for quantum cost, garbage outputs and transistor count. The CN functionality is validated with post-layout simulations, layout versus schematic checks and design rule checks. The proposed CN occupies a post-layout area of 0.013 mm2, achieves up to 4.3 GHz frequency and consumes 52 μ W power. The performance of proposed CN is also compared with its implementation using irreversible gates. The proposed CN achieves about 300% reduction in power delay product with affordable complexity as compared to its classical implementation.

A single clock cycle approximate adder with hybrid prediction and error compensation methods

A single clock cycle approximate adder (SCCA) with hybrid prediction and error compensation methods has been proposed, where the computing accuracy and energy efficiency are carefully balanced. Meanwhile, the addition could be performed in one clock cycle, which decreases the critical path delay and simplify the configuration when applied to a system. Additionally, the proposed adder is able to prevent larger error output in accumulation computing mode. The new approximate adder is applied into the algorithms of Gaussian filter and Convolutional Neural Network (CNN). The simulation results show that the proposed approximate adder achieves 2.8X speedup and 59.9% Power-Delay-Product (PDP) reduction compared with conventional ripple-carry adder (RCA), respectively compared with two outstanding representative approximate adders in [24,28], 19.3% and 2.4% PDP reduction are also achieved with extremely low absolute errors. Our adder shows negligible output quality reduction in image Gaussian filter, where PSNR decreases from 26.74 dB to 26.72 dB; and CNN is also trained successfully using proposed approximate adder with 0.37% and 9.23% accuracy loss in MNIST and CIFAR10 datasets, respectively.

Noise measurement in high-speed domino pseudo-CMOS keeper

Noise immunity is the foremost issue in high-speed domino circuits. In general, better noise immunity is achieved at the cost of speed and power degradation. In this paper, pseudo-dynamic keeper design is proposed to reduce the delay and power with improved noise immunity for domino circuits. The proposed technique is able to achieve reduced delay, power consumption, and better noise immunity by using always ON keeper. The simulation results show that the proposed technique exhibits 41%, 39%, and 19% delay reduction when compared with the low power dynamic circuit for two-input OR gate, two-input EX-OR gate, and 4:1 multiplexer. The proposed logic also performs better as compared to a low power dynamic circuit with 24%, 21%, and 14% reduction in power-delay product for two-input OR gate, two-input EX-OR gate, and four input MUX, respectively. The unity noise gain is also improved as compared to all other existing methods.

Energy efficient design of CNFET-based multi-digit ternary adders

This paper proposes a new technique to implement multi-digit ternary ripple-carry adders in Carbon-nanotube field effect transistor (CNFET) Technology. The proposed multi-digit adder uses efficient half-adders to generate Half-Sum (HS) and Half-Carry (HC). These half-adder outputs (instead of main inputs) are used to compute carry-out at each digit-adder stage using a delay optimized carry generator. The half-sum and carry-out are then used to compute final sum at each digit-adder stage with the help of a sum generator and low-power encoders. Employing delay optimized carry generator along with low-power encoder results in energy efficient multi-digit ternary adder design. Existing and the proposed multi-digit adders of varied operand sizes are implemented in HSPICE. Simulation results show that the proposed multi-digit adder designs result in up to 52% reduction in average power consumption and 58% reduction in Power-Delay Product (PDP), when compared to other multi-digit adders in the literature.