Abstract
Noise immunity is the foremost issue in high-speed domino circuits. In general, better noise immunity is achieved at the cost of speed and power degradation. In this paper, pseudo-dynamic keeper design is proposed to reduce the delay and power with improved noise immunity for domino circuits. The proposed technique is able to achieve reduced delay, power consumption, and better noise immunity by using always ON keeper. The simulation results show that the proposed technique exhibits 41%, 39%, and 19% delay reduction when compared with the low power dynamic circuit for two-input OR gate, two-input EX-OR gate, and 4:1 multiplexer. The proposed logic also performs better as compared to a low power dynamic circuit with 24%, 21%, and 14% reduction in power-delay product for two-input OR gate, two-input EX-OR gate, and four input MUX, respectively. The unity noise gain is also improved as compared to all other existing methods.
Highlights
Static CMOS logic circuits are good in noise immunity
Charge sharing usually happens during the evaluation phase of dynamic logic due to charge distribution in the adjacent dynamic nodes when the pull-down network transistors are ‘‘ON.’’ In general, a keeper circuit is used to diminish the effect of charge sharing and charge leakage
We can observe that pseudo-CMOS keeper (PCK) has 44% reduced delay and power-delay product reduced by 32% as compared with conventional keeper logic for two-input OR gate
Summary
Static CMOS logic circuits are good in noise immunity. the need for higher speed and lower power consumption has created interest to design dynamic logic circuits for the future generation of highperformance ICs. High-speed domino (HSD) keeper[5] circuit is less noise tolerant due to floating nature of dynamic node during the commencement of evaluation phase. At the beginning of the evaluation period, the transistor MP2 is turned OFF During this period, the dynamic node is again floating which causes the circuit to be less noise tolerant. If the evaluation network is OFF, the dynamic node holds logic ‘‘1.’’ This makes the NAND gate output to logic ‘‘0’’ after the two inverter delays and this turns ON the large keeper. The contention current between weak keeper and evaluation network transistors will increase the delay and power consumption. The dynamic node retains its logic ‘‘1’’ through MP2 transistor during its pre-charge phase
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
