Low leakage domino logic circuit for wide fan‐in gates using CNTFET

Abstract

A carbon nanotube field effect transistor (CNTFET) emerged as an alternative to the complementary metal oxide semiconductor (CMOS) for implementing low-power high-speed very-large-scale integration circuits. In this study, the CNTFET technology is discussed that has faster switching speed and high-carrier mobility as compared with the CMOS technology. A new technique ultra-low power dynamic node driven transistor domino logic is proposed for designing low-power domino logic circuits. 2, 4, 8 and 16 input logic gates are simulated using the proposed and existing techniques. Simulation is done on an H-Spice Stanford CNFET 32 nm model at a clock frequency of 200 MHz using the CNTFET technology. The proposed technique shows a maximum power reduction of 57.14% and a maximum delay reduction of 50.24% as compared with the current mirror footed domino logic technique in CNTFET technology. The proposed technique has a maximum power reduction of 96.61% in the CNTFET technology as compared with its counterpart in the CMOS technology for the two-input OR gate. The proposed technique shows a maximum improvement of 1.39× in unity noise gain as compared with the conditional stacked keeper domino logic technique for 16 input OR gates in the CNTFET technology at 200 MHz.