Modified Dual Mode Transmission Gate Diffusion Input Logic for Improving Energy Efficiency

Abstract

This paper presents a modified energy-efficient Dual Mode Transmission Gate Diffusion Input (DMTGDI) design and is termed as M-DMTGDI. A contention issue in dynamic mode operation of existing DMTGDI design and DMPL design is identified and illustrated through mathematical formulation and simulations. To resolve this concern, the pre-charge/pre-discharge transistor in existing DMTGDI design is replaced by dual mode inverter in the proposal. The functional verification and performance comparison of NAND, NOR, XOR gates and 1-bit full adder based on proposed M-DMTGDI is carried out using 90 nm BSIM4 model card for bulk CMOS using Symica DE tool. The performance of the circuits is evaluated in terms of power, delay and Power Delay Product (PDP) in both static and dynamic modes. The variation of PDP with the ratio of the time the circuit is designed to run in dynamic mode against static mode is also investigated to analyze the energy efficiency of the M-DMTGDI design. The proposed approach offers maximum PDP reduction of 33.52%, 99.39% and 96.61% for 2-input gates as compared to their footed DML, DMPL and DMTGDI counterparts, respectively. The reduction in PDP is quite significant in 1-bit full adder circuit where the corresponding values are 94.18%, 99.41% and 99.79%, respectively.