A single clock cycle approximate adder with hybrid prediction and error compensation methods

Abstract

A single clock cycle approximate adder (SCCA) with hybrid prediction and error compensation methods has been proposed, where the computing accuracy and energy efficiency are carefully balanced. Meanwhile, the addition could be performed in one clock cycle, which decreases the critical path delay and simplify the configuration when applied to a system. Additionally, the proposed adder is able to prevent larger error output in accumulation computing mode. The new approximate adder is applied into the algorithms of Gaussian filter and Convolutional Neural Network (CNN). The simulation results show that the proposed approximate adder achieves 2.8X speedup and 59.9% Power-Delay-Product (PDP) reduction compared with conventional ripple-carry adder (RCA), respectively compared with two outstanding representative approximate adders in [24,28], 19.3% and 2.4% PDP reduction are also achieved with extremely low absolute errors. Our adder shows negligible output quality reduction in image Gaussian filter, where PSNR decreases from 26.74 dB to 26.72 dB; and CNN is also trained successfully using proposed approximate adder with 0.37% and 9.23% accuracy loss in MNIST and CIFAR10 datasets, respectively.