Reduction In Power Delay Product Research Articles

Underlap DGMOS for digital-subthreshold operation

Digital circuits operated in the subthreshold region (supply voltage less than the transistor threshold voltage) is suitable for applications requiring ultralow-power and medium frequency of operation. It is also shown that by optimizing the device structure for subthreshold operation, power dissipation can further be reduced. The impact of gate underlap on the effective gate capacitance of double-gate MOS (DGMOS) transistor for digital-subthreshold operation is analyzed in this paper. It shows that with optimum gate underlap, the parasitic fringe capacitances of DGMOS can be significantly reduced resulting in higher performance and lower power consumption. Results on a ring oscillator show that with optimum underlap, 40% improvement in delay can be achieved with 7.3 /spl times/ reduction in power delay product and a 1-bit full-adder circuit can be operated at 1.25 GHz (V/sub dd/=0.2 V) with 6.2 /spl times/ less power than the one with standard (overlap) DGMOS device.

Exploring SOI device structures and interconnect architectures for low-power high-performance circuits

Vertical integration technology offers numerous advantages over conventional structures. Double-gate transistors can be easily fabricated for better device characteristics, and multiple device layers can be vertically stacked for better interconnect performance. In the paper, the authors explore the suitable device structures and interconnect architectures for multi-device-layer three-dimensional (3D) integrated circuits and study how 3D silicon-on-insulator (SOI) circuits can better meet the performance and power dissipation requirements projected by International Technology Roadmap for Semiconductors (ITRS) for future technology generations. Results demonstrate that double-gate SOI circuits can achieve as much as 20% performance gain and 30% power delay product reduction over single-gate SOI. More important, for interconnect-dominated circuits, 3D integration offers significant performance improvement. Compared to 2D integration, most 3D circuits can be clocked at much higher frequencies (double or even triple). 3D circuits, with suitable SOI device structures, can be a viable solution for future low-power high-performance applications.

Design of Si/SiGe heterojunction complementary metal-oxide-semiconductor transistors

An optimized Si/SiGe heterostructure for complementary metal-oxide semiconductor (CMOS) transistor operation is presented. Unlike previous proposals, the design is planar and avoids inversion of the Si layer at the oxide interface. The design consists of a relaxed Si/sub 0.7/Ge/sub 0.3/ buffer, a strained Si quantum well (the electron channel), and a strained S/sub 1-x/Ge/sub x/ (0.7>x>0.5) quantum well (the hole channel). The channel charge distribution is predicted using a 1-D analytical model and quantum mechanical solutions. Transport is modeled using 2-D drift-diffusion and hydrodynamic numerical simulations. An almost symmetric performance of p- and n-transistors with good short-channel behavior is predicted. Simulated ring oscillators show a 4- to 6-fold reduction in power-delay product compared to bulk Si CMOS at the 0.2-/spl mu/m channel length generation.

A model for the dependence of maximum oscillation frequency on collector to substrate capacitance in bipolar transistors

Parasitic effects associated with the collector degrade the frequency performance of a bipolar transistor. These effects include collector series resistance and collector-substrate capacitance. A simple analytical model has been derived to show the dependence of the maximum oscillation frequency f max on these parameters. The significance of using bonded SOI material to reduce collector-substrate capacitance is discussed. The analytical model is used to predict the factor of improvement of this technology over conventional diffusion isolated bulk silicon technology. By considering the impact of process optimisation, an improvement in f max by a factor of between two and three is predicted at maximum power output. By trading off this improvement in f max for lower power operation, it is possible to achieve a significant reduction in power-delay product.