Logically Optimal Novel 4:2 Compressor Architectures for High-Performance Applications

Abstract

Multipliers are principal arithmetic components that play a key role in determining the performance of DSP architectures. While the efficiency of multipliers relies on optimal reduction of partial products within constraint power-delay values, this can be achieved by ‘compressors’ a precisely designed special arithmetic module. In this manuscript, authors propose low-power high-performance 4:2 compressor architectures. The presented designs perform better than the contemporary designs in terms of latency, improved power-delay and area-delay product values. The principal objective of this work is to design and develop a fast 4:2 compressor circuitry with optimal trade-off between power and area by pristine logical decomposition. All the referenced and proposed designs are simulated and synthesized in synopsys design compiler using prelayout CMOS standard cell library of TSMC 65 nm. From the synthesis results, it can be seen that the proposed model provides 12.5–29.17% reduction in area and 7–14.23% reduction in propagation delay with respect to state-of-the-art 4:2 compressor designs. In addition, to estimate the performance stability in realistic applications, 4-bit, 8-bit and 16-bit Dadda multiplier integrated with proposed compressor cells is implemented and verified. The obtained synthesis results substantiate that Dadda multiplier integrated with proposed compressor cells performs better than conventional and state-of-the-art 4:2 compressor-based variants with 4–8% reduction in propagation delay, upto 23.370% reduction in area-delay product and upto 25.62% reduction in power-delay product for 4-bit multiplication, while 6.77–16.85% reduction in propagation delay, 2.62–18.70% reduction in area-delay product and 15.30–23.20% reduction in power-delay product are achieved for 8-bit multiplication. For 16-bit multiplication it shows upto 47.05% reduction in propagation delay, upto 21.68% reduction in area-delay product and upto 24.42% reduction in power-delay product for 16-bit multiplication.