Design of High Speed and Power Efficient Ternary Prefix Adders using CNFETs

Abstract

Ternary logic circuits have advantage over the corresponding binary counterparts with respect to area and interconnect complexity. CNFET technology is ideal to implement ternary logic circuits because the threshold voltage of CNFETs depends on the physical dimensions of their channel. This paper presents the methodology and implementation of ternary prefix adders using CNFETs. While the concept of carry propagate–generate is widely used in the implementation of binary prefix adders, same, however, cannot be directly applied in the implementation of ternary prefix adders. In this paper, a technique that enables the use of carry Propagate-Generate concept in multidigit ternary adders, is proposed. Multidigit ternary prefix adders, which use binary prefix trees for carry computation, are implemented using CNFETs. Five variants of CNFET-based multidigit ternary adders, which use different prefix networks in carry computation, are implemented using HSPICE. Simulation results show that the proposed ternary prefix adders result in up to $58\%$ reduction in average power consumption, $50\%$ reduction in propagation delay and $80\%$ reduction in power-delay product, when compared to other CNFET-based ternary adders existing in the literature.