Performance analysis of conventional and emerging interconnects for low power applications using CMOS and CNFET

Abstract

High resistivity of copper interconnect is bringing on expansive defer and power utilization in the Integrated Circuit at global interconnect length. In this paper we have analyzed the performance of Copper and Carbon Nanotube (CNT) interconnects. CMOS and CNFET device technology is incorporated with Copper (Cu), Single-walled CNT (SWCNT), Multi-Walled CNT (MWCNT), and Mixed CNT Bundle (MCB) interconnect to calculate the propagation delay and Power Delay Product (PDP) of circuit at 32nm technology node. Simulation is done using Driver Interconnect Load (DIL) system in HSPICE. We have found that utilizing CNFET driver, for Intermediate level interconnects, MCB shows 5.5× and 12.9× reduction in propagation delay over copper and SWCNT. Likewise for Global level, Reduction in propagation delay is by 6.6× and 11.1× of MCB over Cu and SWCNT interconnect respectively. Utilizing CNFET driver, copper shows 5.8×, MWCNT shows 9.8× and MCB shows 8× reduction in PDP at local (1µm) interconnect level when compared with copper, MWCNT and MCB interconnects incorporated to CMOS driver. From the simulation results we can conclude that if we utilize CMOS technology, SWCNT is well appropriate for local level interconnect whereas MWCNT and MCB are best reasonable for intermediate and global interconnect however if we utilize CNFET driver, MCB and MWCNT are appropriate for all level of interconnects compared to copper interconnect technology.